VSC8113QB1 VITESSE [Vitesse Semiconductor Corporation], VSC8113QB1 Datasheet - Page 11

• Manufacturer Part Number: VSC8113QB1
• Description: ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery
• Manufacturer: VITESSE [Vitesse Semiconductor Corporation]

VSC8113
G52154-0, Rev 4.2
3/19/99
Data Sheet
Table 4: Transmit Data Input Timing Table (STS-12 Operation)
Table 5: Transmit Data Input Timing Table (STS-3 Operation)
Note: Duty cycle for TXLSCKOUT is 50% +/- 10% worst case
Table 6: Receive Data Output Timing Table (STS-12 Operation)
Parameter
Parameter
Parameter
T
T
T
T
RXCLKIN
T
RXVALID
T
RXLSCK
T
T
T
T
CLKIN
T
T
CLKIN
PROP
INSU
INSU
PROP
INH
INH
PW
RXLSCKOUT
RXOUT [7:0]
RXCLKIN+
RXCLKIN-
Transmit data input byte clock period
Transmit data setup time with respect to TXLSCKIN
Transmit data hold time with respect to TXLSCKIN
Maximum allowable propagation delay for connecting
TXLSCKOUT to TXLSCKIN
Receive clock period
Receive data output byte clock period
Time data on RXOUT [7:0] and FP is valid before and
after the rising edge of RXLSCKOUT
Pulse width of frame detection pulse FP
Transmit data input byte clock period
Transmit data setup time with respect to TXLSCKIN
Transmit data hold time with respect to TXLSCKIN
Maximum allowable propagation delay for connecting
TXLSCKOUT to TXLSCKIN
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
Figure 10: Receive Data Output Timing Diagram
VITESSE
A1
VITESSE SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
T
Description
Description
Description
RXCLKIN
T
RXLSCK
A2
with Integrated Clock Generation and Clock Recovery
ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
A2
Min
Min
Min
1.0
1.0
1.0
1.0
4.0
-
-
-
-
-
-
-
A2
51.44
12.86
12.86
1.608
12.86
Typ
Typ
Typ
-
-
-
-
-
-
-
A2
Max
Max
Max
3.5
30
-
-
-
-
-
-
-
-
-
-
Units
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Page 11