VSC8113QB1 VITESSE [Vitesse Semiconductor Corporation], VSC8113QB1 Datasheet - Page 17

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VSC8113QB1

Manufacturer Part Number
VSC8113QB1
Description
ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery
Manufacturer
VITESSE [Vitesse Semiconductor Corporation]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
VSC8113QB1
Manufacturer:
VTIESSE
Quantity:
20 000
VSC8113
G52154-0, Rev 4.2
3/19/99
Data Sheet
Table 17: Pin Definitions
Package Pin Description
FACLOOP
VDD
CRUEQLP
RESET
LOOPTIM0
B0
B1
B2
VDDP
TXDATAOUT+
TXDATAOUT-
VSS
TXCLKOUT+
TXCLKOUT-
VDDP
N/C
LOSDETEN_
VSS
RXCLKIN+
RXCLKIN-
VDDP
OOF
DSBLCRU
RXDATAIN+
RXDATAIN-
NC
NC
VDD
REFCLKP+
REFCLKP-
Signal
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Pin
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
2
3
4
5
6
7
8
9
VITESSE
VITESSE SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
I/O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
+3.3/+5V
+3.3/+5V
+3.3/+5V
PECL
PECL
PECL
PECL
Level
PECL
PECL
PECL
PECL
PECL
PECL
+3.3V
+3.3V
with Integrated Clock Generation and Clock Recovery
GND
GND
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
Facility loopback, loops high speed receive data and clock
directly to transmit outputs.
+3.3V Power Supply
Loops TXDATAOUT to the CRU replacing RXDATAIN+/-
Resets frame detection, dividers, controls; active high
Enable loop timing operation; active HIGH
Reference clock select, refer to table 12
Reference clock select, refer to table 12
Reference clock select, refer to table 12
+3.3V or +5V Power Supply for PECL I/Os
Transmit output, high speed differential data +
Transmit output, high speed differential data -
Ground
Transmit high speed clock differential output+
Transmit high speed clock differential output-
+3.3V or +5V Power Supply for PECL I/Os
No connection
Enables internal LOS detection (active low).
Ground
Receive high speed differential clock input+
Receive high speed differential clock input-
+3.3V or +5V Power Supply for PECL I/Os
Out Of Frame; Frame detection initiated with high level
Disable on-chip clock recovery unit; active high
Receive high speed differential data input+
Receive high speed differential data input-
No connection
No connection
+3.3V Power Supply
PECL reference clock input+
PECL reference clock input-
Pin Description
Page 17

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