VSC8113QB1 VITESSE [Vitesse Semiconductor Corporation], VSC8113QB1 Datasheet - Page 5

• Manufacturer Part Number: VSC8113QB1
• Description: ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery
• Manufacturer: VITESSE [Vitesse Semiconductor Corporation]

VSC8113
G52154-0, Rev 4.2
3/19/99
Data Sheet
Equipment Loopback
set high, the Equipment Loopback mode is activated and the high speed transmit data generated from the paral-
lel to serial conversion of the low speed data (TXIN[7:0]) is selected and converted back to parallel data in the
receiver section and presented at the low speed parallel outputs (RXOUT[7:0]). See Figure 4. The internally
generated 155/622MHz clock is used to generate the low speed receive clock output (RXLSCKOUT). In Equip-
ment Loopback mode the transmit data (TXIN[7:0]) is serialized and presented at the high speed output
(TXDATAOUT) along with the high speed transmit clock (TXCLKOUT) which is generated by the on-chip
clock multiplier unit.
CRU Equipment Loopback
way back to the high speed I/O. When the CRUEQLP signal is set high, transmit data is looped back to the
CRU, replacing RXDATAIN±
The Equipment Loopback function is controlled by the EQULOOP signal. When the EQULOOP signal is
Exactly the same as equipment loopback, the point where the transmit data is looped back is moved all the
TXDATAOUT
TXCLKOUT
RXDATAIN
FACLOOP
RXCLKIN
TXDATAOUT
TXCLKOUT
EQULOOP
RXDATAIN
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
Recovered
Clock
CRU
Figure 4: Equipment Loopback Data Path
VITESSE
0
1
VITESSE SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
Figure 3: Facility Loopback Data Path
D Q
Q D
D
Q D
Q
0
1
1
0
1
0
with Integrated Clock Generation and Clock Recovery
ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
PLL
Serial to
Parallel
Serial to
Parallel
Parallel to
Serial
Parallel to
Serial
1:8
8:1
1:8
8:1
8
PLL
8
Q D
Q D
D
D
Q
Q
RXOUT[7:0]
RXLSCKOUT
TXIN[7:0]
TXLSCKIN
TXLSCKOUT
RXOUT[7:0]
TXIN[7:0]
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