ADF4150 AD [Analog Devices], ADF4150 Datasheet - Page 23

• Manufacturer Part Number: ADF4150
• Description: Fractional-N/Integer-N PLL Synthesizer
• Manufacturer: AD [Analog Devices]

FAST LOCK—AN EXAMPLE
If a PLL has a reference frequency of 13 MHz, f
and a required lock time of 50 µs, the PLL is set to wide bandwidth
for 40 µs. This example assumes a modulus of 65 for channel
spacing of 200 kHz.
If the time period set for the wide bandwidth is 40 µs, then
Fast Lock Timer Value = Time In Wide Bandwidth × f
Fast Lock Timer Value = 40 µs × 13 MHz/65 = 8
Therefore, 8 must be loaded into the clock divider value in
Register 3 in Step 1 of the sequence described in the Fast Lock
Timer and Register Sequences section.
FAST LOCK—LOOP FILTER TOPOLOGY
To use fast lock mode, the damping resistor in the loop filter
is reduced to ¼ of its value while in wide bandwidth mode. To
achieve the wider loop filter bandwidth, the charge pump
current increases by a factor of 16. To maintain loop stability,
the damping resistor must be reduced a factor of ¼. To enable
fast lock, the SW pin is shorted to the GND pin by settings
Bits[DB16:DB15] in Register 3 to 0, 1. The following two
topologies are available:
•
•
The damping resistor (R1) is divided into two values (R1
and R1A) that have a ratio of 1:3 (see Figure 27).
An extra resistor (R1A) is connected directly from SW,
as shown in Figure 28. The extra resistor is calculated
such that the parallel combination of an extra resistor
and the damping resistor (R1) is reduced to ¼ of the
original value of R1 (see Figure 28).
Figure 27. Fast Lock Loop Filter Topology—Topology 1
Figure 28. Fast Lock Loop Filter Topology—Topology 2
ADF4150
ADF4150
SW
CP
SW
CP
C1
R1A
C1
C2
R1
R1A
R1
C2
R2
R2
C3
PFD
C3
of 13 MHz
VCO
VCO
PFD
/MOD
Rev. 0 | Page 23 of 28
SPUR MECHANISMS
This section describes the three different spur mechanisms that
arise with a fractional-N synthesizer and how to minimize them
in the ADF4150.
Fractional Spurs
The fractional interpolator in the
modulator (SDM) with a modulus (MOD) that is programmable
to any integer value from 2 to 4095. In low spur mode (dither
enabled), the minimum allowable value of MOD is 50. The
SDM is clocked at the PFD reference rate (f
output frequencies to be synthesized at a channel step resolution
of f
In low noise mode (dither off), the quantization noise from the
Σ-Δ modulator appears as fractional spurs. The interval between
spurs is f
in the digital Σ-Δ modulator. For the third-order modulator
used in the ADF4150, the repeat length depends on the value
of MOD, as listed in Table 6.
Table 6. Fractional Spurs with Dither Off
Condition (Dither Off)
If MOD is divisible by 2 but not 3
If MOD is divisible by 3 but not 2
If MOD is divisible by 6
Otherwise
In low spur mode (dither on), the repeat length is extended to
2
quantization error spectrum look like broadband noise. This
may degrade the in-band phase noise at the PLL output by as
much as 10 dB. For lowest noise, dither off is a better choice,
particularly when the final loop bandwidth is low enough to
attenuate even the lowest frequency fractional spur.
Integer Boundary Spurs
Another mechanism for fractional spur creation is the inte-
ractions between the RF VCO frequency and the reference
frequency. When these frequencies are not integer related (the
point of a fractional-N synthesizer) spur sidebands appear on
the VCO output spectrum at an offset frequency that corres-
ponds to the beat note or difference frequency between an
integer multiple of the reference and the VCO frequency. These
spurs are attenuated by the loop filter and are more noticeable
on channels close to integer multiples of the reference where
the difference frequency can be inside the loop bandwidth,
therefore the name integer boundary spurs.
21
PFD
cycles, regardless of the value of MOD, which makes the
/MOD.
PFD
/L, where L is the repeat length of the code sequence
ADF4150
Repeat
Length
2 × MOD
3 × MOD
6 × MOD
MOD
PFD
is a third-order Σ-Δ
) that allows PLL
Spur Interval
Channel step/2
Channel step/3
Channel step/6
Channel step
ADF4150