ADF4208 AD [Analog Devices], ADF4208 Datasheet - Page 5

• Manufacturer Part Number: ADF4208
• Description: Dual RF PLL Frequency Synthesizers
• Manufacturer: AD [Analog Devices]

Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
ADF4206/
ADF4207
V
V
CP
DGND
RF1
OSC
OSC
MUXOUT
CLK
DATA
LE
RF2
DGND
CP
V
V
DD
P
P
DD
1
2
RF1
RF2
1
2
IN
IN
IN
OUT
Mnemonic
RF1
RF2
DGND
MUXOUT
OSC
CP
OSC
RF1
V
DD
V
OUT
RF1
RF1
P
I N
IN
1
1
ADF4208
V
V
CP
DGND
RF1
RF
AGND
OSC
OSC
MUXOUT
CLK
DATA
LE
AGND
RF2
RF2
DGND
CP
V
V
1
2
3
4
5
6
7
8
DD
P
P
DD
1
2
IN
RF1
RF2
(Not to Scale)
1
2
ADF4206/
IN
IN
IN
TOP VIEW
ADF4207
TSSOP
B
IN
OUT
A
B
A
RF1
RF2
RF1
RF2
16
15
14
13
12
11
10
9
Function
Positive Power Supply for the RF1 Section. A 0.1 µF capacitor should be connected between
this pin and the RF1 ground pin, DGND
5.5 V. V
Power Supply for the RF1 Charge Pump. This should be greater than or equal to V
Output from the RF1 Charge Pump. This is normally connected to a loop filter which, in
turn, drives the input to an external VCO.
Ground Pin for the RF1 Digital Circuitry.
Input to the RF1 Prescaler. This low-level input signal is normally taken from the RF1 VCO.
Complementary Input to the RF1 Prescaler of the ADF4208. This point should be decoupled to
the ground plane with a small bypass capacitor.
Ground Pin for the RF1 Analog Circuitry.
Oscillator Input. It has a V
logic gate.
Oscillator Output.
This multiplexer output allows either the IF/RF lock detect, the scaled RF, or the scaled
Reference Frequency to be accessed externally. See Table V.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The
data is latched into the 22-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control
bits. This input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is
loaded into one of the four latches, the latch being selected using the control bits.
Ground Pin for the RF2 Analog Circuitry.
Complementary Input to the RF2 Prescaler. This point should be decoupled to the ground
plane with a small bypass capacitor.
Input to the RF2 Prescaler. This low-level input signal is normally ac-coupled to the
external VCO.
Ground Pin for the RF2, Digital, Interface, and Control Circuitry.
Output from the RF2 Charge Pump. This is normally connected to a loop filter that drives
the input to an external VCO.
Power Supply for the RF2 Charge Pump. This should be greater than or equal to V
Positive Power Supply for the RF2, Interface, and Oscillator Sections. A 0.1 µF capacitor
should be connected between this pin and the RF2 ground Pin, DGND
have a value between 2.7 V and 5.5 V. V
V
V
CP
DGND
RF2
LE
DATA
CLK
DD
P
2
RF2
2
IN
RF2
DD
PIN FUNCTION DESCRIPTIONS
1 must have the same potential as V
PIN CONFIGURATIONS
DD
/2 threshold and can be driven from an external CMOS or TTL
DD
RF1
2 must have the same potential as V
. V
ADF4206/ADF4207/ADF4208
DGND
AGND
MUXOUT
OSC
RF1
RF1
DD
DD
OSC
CP
V
2.
I N
I N
OUT
DD
V
1 should have a value of between 2.7 V and
RF1
RF1
RF1
P
IN
A
B
1
1
10
2
3
4
5
6
7
8
9
1
(Not to Scale)
ADF4208
TOP VIEW
TSSOP
20
19
18
17
16
15
14
13
12
11
AGND
V
V
DGND
RF2
RF2
LE
DATA
CLK
CP
DD
P
2
RF2
2
I N
I N
RF2
RF2
RF2
A
B
. V
DD
DD
2 should
1.
DD
DD
.
.