HD74AC HITACHI [Hitachi Semiconductor], HD74AC Datasheet
HD74AC
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HD74AC Summary of contents
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... HD74AC Series Common Information September 2000 Customer Service Division Semiconductor & Integrated Circuits Hitachi, Ltd. Disclaimer 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. ...
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... I used. HD74ACT is a high-speed CMOS device with a TTL-to-CMOS input buffer stage. These device inputs are designed to interface with TTL outputs operating with 0.4 V, but are functional over the entire FACT operating voltage range of 2.0 to 5.5 VDC. These devices have buffered outputs that will drive CMOS or TTL devices with no additional interface circuitry ...
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FACT Descriptions and Family Characteristics 1.3 Low Power CMOS Operation If there is one single characteristic that justifies the existence of CMOS low power dissipation. In the quiescent state, FACT draws three orders of magnitude less power than ...
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... The balanced output design allows for controlled edge rates and equal rise and fall times. All devices (HD74AC or HD74ACT) are guaranteed to source and sink 24 mA. HD74AC/ACTXXX, are capable of driving 50 transmission lines. ...
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FACT Descriptions and Family Characteristics 1.7.2 Dynamic Output Drive Traditionally, in order to predict what incident wave voltages would occur in a system, the designer was required output analysis using a Bergeron diagram. Not only is this ...
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While this exercise can be done for FACT longer necessary. FACT is guaranteed to drive an incident wave of enough voltage to switch another FACT input –1 –1 0 ...
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... 4 –1 –2 0 –50 –100 Current (mA 150 100 Current (mA 5.5 V and 5 1.65 V, and –150 –200 HD74AC00 –1 – HD74AC00 the ...
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Choice of Voltage Specifications To obtain better performance and higher density, semiconductor technologies are reducing the vertical and horizontal dimensions of integrated device structures. Due to a number of electrical limitations in the manufacture of VLSI devices and the ...
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... V – 0.1 CC 0.5 0.5 0 +1.0 –400 –200 –1.0 –0.4 –0.4 –4 0.37 8.0 8.0 4.0 @ 0.33 V 0.3/0.7 0.4/0.7 1.25/1.25 FAST AS 10.0 FACT HD74AC HD74ACT 2.0 to 6.0 4.5 to 5.5 –40 to +85 –40 to +85 3.15 2.0 1.35 0.8 V – 0.1 V – 0 0.1 0.1 +1.0 +1.0 –1.0 –1.0 – – – – 0 0.37 V 1.25/1.25 0.7/2.4 Unit – ...
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... LS ALS Typ 10.0 5.0 Max 15.0 11.0 Typ 25.0 12.0 Max 40.0 18.0 18.0 10.0 Max 27.0 17.0 = 15pF 10 pF, typ values at 25˚C, max values 70˚C for ALS. L FACT HD74AC HD74ACT Unit 0.0005 mA 0.0025 mW 5.0 ns 0.01 pJ 160 MHz HCMOS FACT unit 8.0 5.0 ns 23.0 8.5 ns 14.0 8.0 ns 40.0 10.5 ns 18.0 5.0 ns 40.0 10 ...
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FACT Descriptions and Family Characteristics 2. Circuit Characteristics 2.1 Power Dissipation One advantage to using CMOS logic is its extremely low power consumption. During quiescent conditions, FACT will consume several orders of magnitude less current than its bipolar counterparts. But ...
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SET Q D Input ’74 Q CLK CLR Figure 9 Power Demonstration Circuit Schematic 3. The power supply current is measure and recorded at input frequencies of 200 kHz and 1 MHz. 4. The power dissipation capacitance is calculated by ...
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... HD74AC138/74ALS138 decoder. This generated eight non-overlapping clock pulses on the outputs of the HD74AC138/74ALS138, which were then connected to an HD74AC04/74ALS04 inverter. The input frequency was then varied and the power consumption was measured. Figure 10 illustrates the results of these measurements. ...
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... FACT devices 3.0 Figure 11 Propagation Delay vs. V FACT Descriptions and Family Characteristics 4 and lumped load capacitance (C CC Delay (ns) 3.5 4.0 4.5 V (Volts) CC 5.5 Units 19 ps/pF 12.5 ps/pF ). Figures 13 and 14 show the L 5.0 5.5 6.0 (HD74AC00 ...
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... Figure 12 Propagation Delay vs Delay (ns) t PLH PLH PLH PHL Load Capacitance (pF Load Capacitance (pF) Figure 13 t vs. Capacitance rise t PHL PHL (HD74AC00 5. ...
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Figure 15 CMOS Inverter Cross Section with Latch-up Circuit Schematic 2.3 Latch-up A major problem with CMOS has been its sensitivity to latch-up, usually attributed to high parasitic gains and high input impedance (figure 15). FACT logic is guaranteed ...
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FACT Descriptions and Family Characteristics 2.4 Electrostatic Discharge (ESD) Sensitivity FACT circuits show excellent resistance to ESD-type damage. These logic devices are classified as category ‘B’ of MIL-STD-883C, test method 3015, and withstand 4000 V typically. FACT logic is guaranteed ...
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FACT Descriptions and Family Characteristics 100% 90% 36.8% 10% t RISE t t PEAK DECAY TIME Figure 17 ESD Pulse Waveform RISE t 350 ns DECAY ( 300 ...
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Definition of Specifications 1. Power Dissipation-Test Philosophy In an erfort to reduce confusion about measuring C has been adopted, which specifies the test setup for each type of device. This allows a device to be exercised in a consistent manner ...
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Ratings and Specifications Table 1 Absolute Maximum Ratings Parameter Symbol Supply voltage input Diode current input voltage output Diode I OK current or DC output voltage ...
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... Definition of Specifications Table 3 DC Characteristics for HD74AC Family Devices Parameter Symbol V Minimum V 3.0 IH High Level Input 4.5 Voltage 5.5 Maximum V 3.0 IL Low Level Input 4.5 Voltage 5.5 Maximum V 3.0 OH High Level 4.5 Output Voltage 5.5 3.0 4.5 5.5 Maximum V 3.0 OL Low Level 4.5 Output Voltage 5.5 3.0 4.5 5.5 Maximum I 5.5 IN Input Leakage Current Maximum I 5 ...
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... Table 4 DC Characteristics for HD74ACT Family Devices Parameter Symbol V Minimum High V 4.5 IH Level Input 5.5 Voltage Maximum Low V 4.5 IL Level Input 5.5 Voltage Maximum High V 4.5 OH Level 5.5 Output Voltage 4.5 5.5 Maximum Low V 4.5 OL Level Output 5.5 Voltage 4.5 5.5 Maximum I 5.5 IN Input Current Maximum 3- I 5.5 OZ State Current ...
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... Loading Circuit Figure 1 shows the AC loading circuit used in characterizing and specifying propagation delays of all FACT devices (HD74AC and HD74ACT) unless otherwise specified in the data sheet of a specific device. The use of this load, differs somewhat from previous practice provides more meaningful information and minimizes problems of instrumentation and customer correlation. In the past, +25 C propagation delays for TTL devices were specified with a load ground ...
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... AC Test Input Levels Input Range Figure 2b Test Input Signal Levels (cont) HD74ACXX Devices DC LOW LOW Level Noise Input Range Immunity Figure 2a Test Input Signal Levels HD74ACTXX Devices DC LOW LOW Level Noise Input Range Immunity Definition of Specifications DC HIGH HIGH Level Noise Immunity ...
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... CC 3.3 Rise and Fall Times Input signals should have rise and fall times of 3.0 ns and signal swing 3.0 V for HD74ACT devices for HD74ACT devices. Rise and fall times less than or equal should be used ...
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... Two pulse generators are usually required for testing such parameters as setup time, hold time, max recovery time etc. Vmi = 50% V for HD74AC devices; 1.5 V for HD74ACT devices CC Vmo = 50% V for HD74AC/HD74ACT devices CC Figure 3 Waveform for Inverting and Non-Inverting Functions and ground leads with a finite inductance ...
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... Disable times to device worst case timing signals to ensure that the output of one device is disabled befor that of another device is enabled. OUTPUT CONTROL DATA OUT Vmi = 50% V for HD74AC devices; 1.5 V for HD74ACT devices CC Vmo = 50% V for HD74AC/HD74ACT devices CC Figure 5 3-State Output High Enable and Disable Times 26 ...
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... Ensure that all plastic parts of the tester, that are near the device, are conductive and connected to ground. DATA IN CONTROL INPUT MR OR CLEAR Vmi = 50% V for HD74AC devices; 1.5 V for HD74ACT devices CC Vmo = 50% V for HD74AC/HD74ACT devices CC Figure 7 Setup Time, Hold Time and Recovery Time Definition of Specifications Vmi t ...
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... Definition of Specifications 4. Symbols and Terms Defined for HD74AC Series Explanation of Symbols Used in Electrical Characteristics and Recommended Operating Conditions Table 5 DC Characteristics Symbol Term V High level input voltage IH V Low level input voltage IL V Low level output voltage OL V High level output voltage ...
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Table 6 AC Characteristics Symbol Term f Maximum clock frequency max t Rise (transient) time TLH t Fall (transient) time THL t Output rise propagation delay time PLH t Output fall propagation delay time PHL t 3-state output disable time ...
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Definition of Specifications Symbol Term t Recovery time rec C Input capacitance IN C Power Dissipation Capacitance PD Table 7 Explanation of Symbols Used in Function Tables Symbol Description H High level (in steady state; written H or "H" level ...
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Today’s system designer is faced with the problem of keeping ahead when addressing system performance and reliability. Hitachi’s Advanced CMOS helps designers achieve these goals. FACT (Fairchild Advanced CMOS Technology) logic was designed to alleviate many of the drawbacks that ...
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... These interfaces tend to be slightly slower than their CMOS-level counter-parts due to an extra buffer stage required for level conversion approximately 4 which is depicted in figure 2. The correct CC TTL Figure 2 V Pull-Up on TTL Outputs TTL Figure 3 TTL Interfacing to HD74ACT NMOS, CMOS or TTL AC ACT ...
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... ECL logic is illustrated in figure 4. Figures 5 and 6 show the translation from ECL-to-FACT, which is somewhat more complicated. These two examples offer some possible interfaces between ECL and FACT logic. AC/ACT Figure 4 Resistive FACT-to-ECL Translation T1,T2 - 2SC641 (K) D1,D2 - HP5082 - 2811 Figure 5 Single-Ended ECL-to-HD74AC Circuit of approximately 4 The CC +5V 560 510 470 – ...
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... CMOS structure to be conducting. This will cause a low resistive path from the supply rail to ground, increasing the power consumption by several orders of magnitude important that CMOS inputs are always driven as close as possible to the rail. Figure 7 Crystal Oscillator Circuit Implemented with FACT HD74AC00 34 510 ...
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Line Driving With the available high-speed logic families, designers can reach new heights in system performance. Yet, these faster devices require a closer look at transmission line effects. Although all circuit conductors have transmission line properties, these characteristics become ...
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Design Considerations There are several termination schemes which may be used (figure 8). Included are series, parallel, AC parallel and Thevenin terminations. AC parallel and series terminations are the most useful for low power applications since they do not consume ...
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Parallel Termination Parallel terminations are not generally recommended for CMOS circuits due to their power consumption, which can exceed the power consumption of the logic itself. The power consumption of parallel terminations is a function of the resistor value ...
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Design Considerations 3. CMOS Bus Loading CMOS logic devices have clamp diodes from all inputs and outputs to V increase system reliability by damping out undershoot and overshoot noise, they can cause problems if power is lost. Figure 10 exemplifies ...
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Crosstalk The problem of crosstalk and how to deal with it is becoming more important as system performance and board densities increase. Crosstalk is the capacitive coupling of signals from one line to another. The amplitude of the noise ...
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Design Considerations 0.0 V Key This figure shows traces taken on a test fixture designed to exaggerate the amplitude of crosstalk pulses. Figure 12 Reverse Crosstalk on PCB Traces 40 Time (ns) (5.0 ns/div) Vertical Scale Active Driver 1.0 V/Div ...
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Gnd With over 2 noise margins, the FACT family offers better noise rejection than any other comparable technology. In any design, the distance that lines run adjacent to each other should be kept as short as possible. The ...
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Design Considerations 4.2 Ground Bounce Ground bounce occurs as a result of the intrinsic characteristics of the leadframes and bondwires of the packages used to house CMOS devices. As edge rates and drive capability increase in advanced logic families, the ...
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The three waveforms shown in figure 16 depict how ground bounce is generated. The first waveform shows the voltage (V) across the load switched from a logic high to a logic low. The output slue rate is ...
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... This drooping of rails will cause the rise and fall times to become elongated. Consider the example described in figure 18 to calculate the amount of decoupling necessary. This circuit utilizes an HD74AC240 driving a 100 Being in the middle of the bus, the driver will see two 100 switch the line from rail to rail, a drive needed ...
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V 1/16" Glass Epoxy Ground Plane a) 50 Impedance V CC Gnd 032 Epoxy Glass Impedance Data Bus 100 Buffer 100 V CC Bypass Capacitors Specify V Place one decoupling capacitor adjacent to ...
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... The FACT product line is composed of two types of advanced CMOS circuits: HD74AC and HD74ACT devices. HD74ACT indicates an advanced CMOS device with TTL-type input thresholds for direct replacement of LS and ALS circuits. As this HD74ACT series is used to replace TTL, the Delta I specification must be considered; this spec may be confusing and misleading to the engineer unfamiliar with CMOS ...
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... Fortunately, there are several factors which tend to reduce the increase in I will be able to drive FACT inputs well beyond the TTL output specification due to FACT’s low input loading in a typical system. For example, FAST logic outputs can drive HD74ACT-type inputs down to 200 mV and up to 3.5 V. Additionally, the typical I limit ...
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... I is being measured by the tester. When testing the CMOS HD74AC245/HD74ACT245, problems can arise depending upon how the CC test is conducted. Note the structure of the HD74AC245/HD74ACT245’s I/O pins illustrated figure 23. 10.00 0.00 Figure 23 HD74AC245/HD74ACT245 I/O Structure 48 test ...
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Each I/O pin is connected to both an input device and an output device. The pin can be viewed as having three states: input, output and output disabled. However, only two states actually exist. The pin is either an input ...
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Design Considerations 8. Testing Disable Times of 3-State Outputs in a Transmission Line Environment Traditionally, the disable time of a 3-state buffer has been measured from the 50% point on the disable input, to the 10% or 90% point on ...
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This current wave will propagate down the line where it will encounter the high impedance tester load. This will cause ...