HD74AC HITACHI [Hitachi Semiconductor], HD74AC Datasheet - Page 16

• Manufacturer Part Number: HD74AC
• Description: HD74AC Series Common Information
• Manufacturer: HITACHI [Hitachi Semiconductor]

2.3 Latch-up
A major problem with CMOS has been its sensitivity to latch-up, usually attributed to high parasitic gains
and high input impedance (figure 15). FACT logic is guaranteed not to latch-up with dynamic currents of
100 mA forced into or out of the inputs or the outputs under worst case conditions (Ta = 85˚C and V
5.5 VDC). At room temperature the parts can typically withstand dynamic currents of over 450 mA. For
most designs, latch-up will not be a problem, but the designer should be aware of its causes and how to
prevent it.
FACT devices have been specifically designed to reduce the possibility of latch -up occurring; Hitachi
accomplished this by lowering the gain of the parasitic transistors, reducing N-well and p-well resistivity to
increase external drive current required to cause a parasitic to turn on, and careful design and layout to
minimize the substrate-injected current coupling to other circuit areas.
Figure 15 CMOS Inverter Cross Section with Latch-up Circuit Schematic
+V
10
DD
N-well
9
8
7
6
5
4
3
2
1
0
N+
P-Channel MOS
P+
FACT Descriptions and Family Characteristics
Figure 14 t
N-Substrate
10
Load Capacitance (pF)
P+
Output
fall
20
Input
vs. Capacitance
N-Channel MOS
N+
30
V
Ta = 25 C
CC
= 5.0V
N+ P+
40
P-well
-V
SS
50
CC
=
15