CAT9532 ONSEMI [ON Semiconductor], CAT9532 Datasheet - Page 8

• Manufacturer Part Number: CAT9532
• Description: 16-bit Programmable LED Dimmer with I2C Interface
• Manufacturer: ONSEMI [ON Semiconductor]

CAT9532
Acknowledge
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8
bits of data. The SDA line remains stable LOW during
the HIGH period of the acknowledge related clock
pulse (Figure 4).
The CAT9532 responds with an acknowledge after
receiving a START condition and its slave address. If
the device has been selected along with a write
operation, it responds with an acknowledge after
receiving each 8- bit byte.
When the CAT9532 begins a READ mode it transmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT9532 will continue to transmit
data. If no acknowledge is sent by the Master, the
device terminates data transmission and waits for a
STOP condition. The master must then issue a stop
condition to return the CAT9532 to the standby power
mode and place the device in a known state.
Registers and Bus Transactions
After the successful acknowledgement of the slave
address, the bus master will send a command byte to
the CAT9532 which will be stored in the Control
Register. The format of the Control Register is shown
in Figure 5.
Figure 4. Acknowledge Timing
Figure 5. Control Register
Doc. No. MD-9001 Rev. E
FROM TRANSMITTER
FROM RECEIVER
DATA OUTPUT
DATA OUTPUT
SCL FROM
MASTER
RESET STATE: 00h
START
0
0
AUTO-INCREMENT FLAG
1
0
8
AI
The Control Register acts as a pointer to determine
which register will be written or read. The four least
significant bits, B0, B1, B2, B3, are used to select
which
to the Table 1.
If the auto increment flag (AI) is set, the four least
significant
automatically incremented after a read or write
operation. This allows the user to access the
CAT9532 internal registers sequentially. The content
of these bits will rollover to “0000” after the last
register is accessed.
Table 1. Internal Registers Selection
B3
0
0
0
0
0
0
0
0
1
1
B3
REGISTER ADDRESS
B2
0
0
0
0
1
1
1
1
0
0
internal
B2
B1
0
0
1
1
0
0
1
1
0
0
bits
8
B1
B0
0
1
0
1
0
1
0
1
0
1
register
ACKNOWLEDGE
of
B0
Register
Name
INPUT0
INPUT1
PSC0
PWM0
PSC1
PWM1
LS0
LS1
LS2
LS3
the
9
Characteristics subject to change without notice
is accessed,
Control
Type
READ
READ
READ/
WRITE
READ/
WRITE
READ/
WRITE
READ/
WRITE
READ/
WRITE
READ/
WRITE
READ/
WRITE
READ/
WRITE
© 2010 SCILLC. All rights reserved
Register
Register
Function
Input
Register 0
Input
Register 1
Frequency
Prescaler 0
PWM
Register 0
Frequency
Prescaler 1
PWM
Register 1
LED 0-3
Selector
LED 4-7
Selector
LED 8-11
Selector
LED 12-15
Selector
according
are