AD9915 AD [Analog Devices], AD9915 Datasheet - Page 44

• Manufacturer Part Number: AD9915
• Description: 2.5 GSPS Direct Digital Synthesizer with 12-Bit DAC
• Manufacturer: AD [Analog Devices]

Control Function Register 4 (CFR4)—Address 0x03
Table 20. Bit Descriptions for DAC
Bit(s)
[31:27]
26
25
24
[23:0]
Digital Ramp Lower Limit Register—Address 0x04
This register is effective only if the digital ramp enable bit in the CFR2 register (0x01[19]) = 1. See the Digital Ramp Generator (DRG)
section for details.
Table 21. Bit Descriptions for Digital Ramp Lower Limit Register
Bit(s)
[31:0]
Digital Ramp Upper Limit Register—Address 0x05
This register is effective only if the digital ramp enable bit in the CFR2 register (0x01[19]) = 1. See the Digital Ramp Generator (DRG)
section for details.
Table 22. Bit Descriptions for Digital Ramp Limit Register
Bit(s)
[31:0]
Rising Digital Ramp Step Size Register—Address 0x06
This register is effective only if the digital ramp enable bit in the CFR2 register (0x01[19]) = 1. See the Digital Ramp Generator (DRG)
section for details.
Table 23. Bit Descriptions for Rising Digital Ramp Step Size Register
Bit(s)
[31:0]
Falling Digital Ramp Step Size Register—Address 0x07
This register is effective only if the digital ramp enable bit in the CFR2 register (0x01[19]) = 1. See the Digital Ramp Generator (DRG)
section for details.
Table 24. Bit Descriptions for Falling Digital Ramp Step Size Register
Bit(s)
[31:0]
AD9915
Mnemonic
Open
Auxiliary divider power-
down
DAC CAL clock power-own
DAC CAL enable
(See description)
Mnemonic
Digital ramp lower limit
Mnemonic
Digital ramp upper limit
Mnemonic
Rising digital ramp
increment step size
Mnemonic
Falling digital ramp
decrement step size
Description
Open.
0 = enables the SYNC OUT circuitry.
1 = disables the SYNC OUT circuitry
0 = enables the DAC CAL clock if Bit 26 in Register 0x03 is Logic 0.
1 = disables the DAC CAL clock.
1 = initiates an auto DAC calibration. The DAC CAL calibration is required at power-up and
any time the internal system clock is changed.
These bits must always be programmed with the default values listed in the default column
in Table 16.
Description
32-bit digital ramp lower limit value.
Description
32-bit digital ramp upper limit value.
Description
32-bit digital ramp increment step size value.
Description
32-bit digital ramp decrement step size value.
Rev. A | Page 44 of 48
Data Sheet