PCA8534AH-Q900 NXP [NXP Semiconductors], PCA8534AH-Q900 Datasheet - Page 18

• Manufacturer Part Number: PCA8534AH-Q900
• Description: Universal LCD driver for low multiplex rates
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCA8534A_2
Product data sheet
7.13 Output bank selector
7.14 Input bank selector
7.15 Blinker
This last step is very important because during writing data to the first PCA8534A, the
data pointer of the second PCA8534A is incremented. In addition, the hardware
subaddress should not be changed whilst the device is being accessed on the I
interface.
The output bank selector (see
address for transfer to the display register. The actual row selected depends on the LCD
drive mode in operation and on the instant in the multiplex sequence.
The SYNC signal resets these sequences to the following starting points: row 3 for
1:4 multiplex, row 2 for 1:3 multiplex, row 1 for 1:2 multiplex and row 0 for static mode.
The PCA8534A includes a RAM bank switching feature in the static and 1:2 multiplex
drive modes. In static drive mode, the bank-select command may request the contents of
row 2 to be selected for display instead of the contents of row 0. In 1:2 multiplex drive
mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This
enables preparation of display information in an alternative bank and the ability to switch
to it once it has been assembled.
The input bank selector loads display data into the display RAM in accordance with the
selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode
or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command. The
input bank selector functions independently to the output bank selector.
The display blinking capabilities of the PCA8534A are very versatile. The whole display
can be blinked at frequencies set by the blink-select command (see
blinking frequencies are fractions of the clock frequency. The ratios between the clock and
blinking frequencies depend on the mode in which the device is operating (see
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In 1:4 multiplex mode: all RAM addresses of row 0 are selected, followed sequentially
by the contents of row 1, row 2, and then row 3.
In 1:3 multiplex mode: rows 0, 1, and 2 are selected sequentially.
In 1:2 multiplex mode: rows 0 and 1 are selected.
In the static mode: row 0 is selected.
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 1 June 2010
Table
14), selects one of the four rows per display RAM
Universal LCD driver for low multiplex rates
PCA8534A
Table
© NXP B.V. 2010. All rights reserved.
15). The
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C-bus
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