M41T00AUD_12 STMICROELECTRONICS [STMicroelectronics], M41T00AUD_12 Datasheet
M41T00AUD_12
Related parts for M41T00AUD_12
M41T00AUD_12 Summary of contents
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Features Combination real-time clock with audio ■ Serial real-time clock (RTC) based on M41T00 ■ Audio section provides: – 300 mW differential audio amplifier – 256 and 512 Hz tone generation – –33 to +12 dB gain steps ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M41T00AUD 8 Initial conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M41T00AUD List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Description 1 Description The M41T00AUD is a low-power serial real-time clock (RTC) with an integral audio section with tone generator and 300 mW output amplifier. The RTC is a superset of the M41T00 with enhancements such as a precision reference ...
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M41T00AUD 2 Pin settings 2.1 Pin connection Figure 2. Pin connection 2.2 Pin description Table 1. Pin description V CC OSCI OSCO SCL SDA AIN V BIAS V SS AOUT– AOUT+ IRQ/FT/OUT V BACK FBK NC No name; exposed pad ...
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Application 3 Application Figure 3. Application diagram 8/ AUTOMATIC BATTERY V INT SWITCHOVER & DESELEC T REFERENCE V PFD =2.80V WRITE uC (SDA, PROTECT SCL 400kHz I 2 ...
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M41T00AUD Figure 4. Typical hookup example 3.3V SCL SDA 32.768 kHz R2 should be a minimum Audio In Set R1’ for unity gain Optional: can sum additional audio inputs 3.3 V Place near ...
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Operation 4 Operation The M41T00AUD clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 10 bytes contained in the device can then be ...
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M41T00AUD 4.1 2-wire bus characteristics This bus is intended for communication between different ICs. It consists of two lines: one bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the SCL lines must be ...
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Operation Figure 5. Serial bus data transfer sequence CLOCK DATA START CONDITION Figure 6. Acknowledgement sequence SCLK FROM MASTER DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER Figure 7. Bus timing requirements sequence SDA t BUF SCL P Note: P ...
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M41T00AUD 4.2 Characteristics Table 3. AC characteristics Symbol f SCL clock frequency SCL t Clock low period LOW t Clock high period HIGH t SDA and SCL rise time R t SDA and SCL fall time F START condition hold ...
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Operation Figure 8. Slave address location START Figure 9. READ mode sequence BUS ACTIVITY: MASTER SDA LINE S BUS ACTIVITY: SLAVE ADDRESS DATA n+X Figure 10. Alternate READ mode sequence BUS ACTIVITY: MASTER SDA LINE S BUS ACTIVITY: SLAVE ADDRESS ...
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M41T00AUD 4.4 WRITE mode In this mode the master transmitter transmits to the M41T00AUD slave receiver. Bus protocol is shown in (R placed on the bus and indicates to the addressed device that word address An will ...
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M41T00AUD clock operation 5 M41T00AUD clock operation 5.1 Clock registers The 10-byte register map (see and time from the clock binary coded decimal format. Seconds, minutes, and hours are contained within the first three registers. Bits D6 to ...
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M41T00AUD Register 08 is the calibration register. Calibration is described in detail in the clock calibration section. Bit D7 is the OUT bit and controls the discrete output pin IRQ/FT/OUT as described in Table 5.1.1 Halt bit operation Bit D7 ...
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M41T00AUD clock operation 5.2 Reading and writing the clock registers The counters used to implement the timing chain in the real-time clock are not directly accessed by the serial interface. Instead, as depicted in buffered through a set of transfer ...
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M41T00AUD Table 4. M41T00AUD register map Addr 00h ST 10 seconds (2) 0 01h 10 minutes 02h CEB CB 10 hours (3) Y 03h 0 Y 04h 0 0 05h 06h 10 years 07h ...
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M41T00AUD clock operation Figure 12. Counter update diagram SERIAL BUS 20/42 READ/WRITE BUFFER TRANSFER REGISTERS REGISTER REGISTER REGISTER SERIAL TRANSFER REGISTER REGISTER REGISTER REGISTER REGISTER Doc ID 13480 Rev 5 M41T00AUD 32KHz OSC DIVIDE BY 32768 1 ...
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M41T00AUD 5.3 Priority for IRQ/FT/OUT pin Three functions share pin 5 of the M41T00AUD. The oscillator fail interrupt (IRQ), the calibration frequency test output (FT) and the discrete logic output (OUT) all use this pin. In normal operation, when operating ...
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M41T00AUD clock operation 5.4 Switchover thresholds While the M41T00AUD includes a precision reference for the backup switchover threshold not a fixed value, but depends on the backup voltage, V switchover at the lesser of the reference voltage (V ...
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M41T00AUD 5.5 Trickle charge circuit The M41T00AUD includes a trickle charge circuit to be used with a backup capacitor illustrated in Figure supply input. (The input nature is not depicted in the figure.) The trickle charge output function ...
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Clock calibration 6 Clock calibration The M41T00AUD oscillator is designed for use with a 12.5 pF crystal load capacitance. With a nominal ±20 ppm crystal, the M41T00AUD will be accurate to ±35 ppm. When the calibration circuit is properly employed, ...
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M41T00AUD Example 2: Sign is 0 and (00010b). The 16-minute interval will be 513 + (60-3) * 512 + 512 = 491523 cycles long out of a possible 512 * 60 ...
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Clock calibration Table 6. Digital calibration values Calibration value DC4-DC0 Decimal Binary 0 00000 1 00001 2 00010 3 00011 4 00100 5 00101 6 00110 7 00111 8 01000 9 01001 10 01010 11 01011 12 01100 13 01101 ...
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M41T00AUD Figure 15. Crystal accuracy across temperature Frequency (ppm –20 –40 –60 –80 –100 –120 –140 –160 –40 – – –0.036 ppm/˚C 2 ± 0.006 ppm/˚ ...
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Audio section operation 7 Audio section operation The audio section is comprised of five main parts. The input includes a summing amplifier. A minimum 10 kΩ feedback resistor is required. With that and 20 kΩ input resistors, the input signals ...
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M41T00AUD Table 7. MUTE and GAIN MUTE Binary 1 XXXX 0 1111 0 1110 0 1101 0 1100 0 1011 0 1010 0 1001 0 1000 0 0111 0 0110 0 0101 0 0100 0 0011 0 0010 0 0001 ...
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Audio section operation 7.1 Gain The programmable gain stage follows the band pass filter. It provides between –33 and + gain steps (+/-1 dB per step). The gain is selected by the GAIN bits, D3- ...
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M41T00AUD The other parameter pertains to the gain step size, a relative measurement shown in Table 16 as 3±1 dB. For any gain setting in guaranteed to be between 2 and 4 dB higher (or lower). For example, ...
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Initial conditions 8 Initial conditions The first time the M41T00AUD is powered up, some of its registers will automatically have their bits set to pre-determined levels as depicted in the set to benign levels to ensure predictable operation of the ...
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M41T00AUD 9 Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions ...
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DC and AC parameters 10 DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived ...
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M41T00AUD Table 12. DC characteristics Symbol Parameter I Input leakage current LI I Output leakage current LO I Active supply current CC1 I Standby supply current CC2 V Input low voltage IL V Input high voltage IH Output low voltage ...
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DC and AC parameters Figure 18. Power down/up mode AC waveforms SDA SCL Table 14. RTC power down/up AC characteristics Symbol t SCL and SDA at VIH before power-down PD t SCL and SDA ...
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M41T00AUD 11 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ...
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Package mechanical data Figure 19. DFN16 ( mm) package outline Note: Drawing is not to scale. Table 17. DFN16 ( mm) package mechanical data Sym ...
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M41T00AUD Figure 20. DFN16 ( mm) footprint Doc ID 13480 Rev 5 Package mechanical data 7964660_B 39/42 ...
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Part numbering 12 Part numbering Table 18. Ordering information scheme Example: Device type M41T00AUD Package D = Lead-free DFN Temperature range ° °C Shipping method ® ECOPACK lead-free ...
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M41T00AUD 13 Revision history Table 19. Document revision history Date 01-May-2007 13-Dec-2007 01-Dec-2008 06-Mar-2009 06-Feb-2012 Revision 1 Initial release. 2 Minor text changes; updated footnote Minor reformatting; updated 4 Updated text in Section 11: Package mechanical footprint ...
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Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any ...