M41T00AUD_12 STMICROELECTRONICS [STMicroelectronics], M41T00AUD_12 Datasheet - Page 30

• Manufacturer Part Number: M41T00AUD_12
• Description: Serial real-time clock (RTC) with audio
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Audio section operation
7.1
7.1.1
30/42
Gain
The programmable gain stage follows the band pass filter. It provides between –33 and
+12 dB of gain, in 3 dB steps (+/-1 dB per step). The gain is selected by the GAIN bits, D3-
D0 of register 08h, as listed in
audio to be cut off altogether.
At the first power-up, GAIN will be initialized to its lowest value, 0, corresponding to a gain of
–33 dB. Furthermore, MUTE will be set thus cutting off all audio.
On subsequent power-ups, GAIN is unaffected, but the MUTE bit is always set to turn off the
audio at power-up.
The final section is the output driver. It has a differential output capable of driving 300mW
into an 8 Ω load.
The overall gain of the M41T00AUD is defined as the ratio of the AC output voltage, A
and the AC input voltage, S
blocks any DC in the input signal.
Equation 1
A
Each of the output levels is determined by the ratio of the feedback and input resistors along
with the GAIN value.
where A
yields:
With R1 = 2*R2, this reduces to A
Table 7
indicated 0.1 uF capacitor). For GAIN set to B (0 dB, A
equal to the input (
Gain tolerance
Two tolerance parameters apply to the gain levels. As shown in
limits are listed for four of the GAIN values (4, 5, Bh and Eh). For GAIN=Bh, the tolerance is
±1 dB. This means the end-to-end gain of the part, with R1 = 2*R2, will be 0±1 dB. For
GAIN = 4, 5 and Eh, the tolerance is ±2 dB. At each of these three settings, as shown in
table 7, the gain will be within 2 dB of the listed typical value. For GAIN =E, the end-to-end
gain will be between +7 and +11 dB (9±2 dB).
OUT
is measured between the output pins AOUT
reflect overall gain of the circuit (at mid-band frequencies, about 1kHz with the
V
is the scalar gain as shown in
A
OUT
= S
±
1 dB).
IN
x A
V
IN
x R2/R1
, as shown in
Doc ID 13480 Rev 5
Table
AOUT
Overall gain = A
AOUT
A
OUT
OUT
4. A MUTE bit, D4 of the same register, allows the
-
–
= S
+
(
= AOUT
-
=
= S
Table
S
IN
-
IN
S
Figure
IN
x A
IN
x A
x A
7. Substituting these into Equation 1 above
x A
V
+
V
. Thus, when R1 = 2*R2, the gain levels in
OUT
-
V
x R2/R1) = 2 S
+
V
16. The 0.1 uF input coupling capacitor
AOUT
x R2/R1
and AOUT
x R2/R1
/ S
V
IN
= 1), the output voltage will be
–
–
.
Table
IN
x A
V
7, upper and lower
x R2/R1
M41T00AUD
OUT
,