AD7367-5ARUZ-REEL7 AD [Analog Devices], AD7367-5ARUZ-REEL7 Datasheet - Page 10

• Manufacturer Part Number: AD7367-5ARUZ-REEL7
• Description: True Bipolar Input, Dual 1us, 14-Bit, 2-Channel SAR ADC
• Manufacturer: AD [Analog Devices]

AD7367
PSRR (Power Supply Rejection)
Variations in power supply affect the full-scale transition but
not the converter’s linearity. Power supply rejection is the
maximum change in the full-scale transition point due to a
change in power supply voltage from the nominal value (see
figure x).
THEORY OF OPERATION
Circuit Information
The AD7367 is a fast, dual, 2-Channel, 14-bit, Bipolar Input,
Serial A/D converter. The AD7367 can accept bipolar input
ranges of ±10V and ±5V. It can also accept a 0 to 10V unipolar
input range. The AD7367 requires V
the high voltage analog input structure. These supplies must be
equal to or greater than 11.5V. See Table 6 for the minimum
requirements on these supplies for each Analog Input Range.
The AD7367 requires a low voltage 4.75V to 5.25 V V
to power the ADC core.
Table 6. Reference and Supply Requirements for each Analog
Input Range
The AD7367 contains two on-chip differential track-and-hold
amplifiers, two successive approximation A/D converters, and a
serial interface with two separate data output pins. It is housed
in a 24-lead TSSOP package, offering the user considerable
space-saving advantages over alternative solutions. The AD7367
requires a
edge of
mode and the conversions are initiated. The BUSY signal will go
high to indicate the conversions are taking place. The clock
source for each successive approximation ADC is provided by
an internal oscillator. The BUSY signal will go low to indicate
the end of conversion. On the falling edge of BUSY the track-
and-hold will return to track mode. Once the conversion is
finished, the serial clock input accesses data from the part.
The AD7367 has an on-chip 2.5 V reference that can be
overdriven when an external reference is preferred. If the
internal reference is to be used elsewhere in a system, then the
output from D
Selected
Analog
Input
Range (V)
0 to 10
±10
± 5
CONVST
CONVST
Reference
Voltage
(V)
2.5
3.0
2.5
3.0
2.5
3.0
CAP
both track-and-holds will be placed into hold
A & D
signal to start conversion. On the falling
CAP
B must first be buffered. On Power
Full
Scale
Input
Range(V)
±10
±12
±5
±6
0 to 10
0 to 12
DD
and V
5
5
5
5
5
5
AV
(V)
CC
SS
dual supplies for
±11.5
±12
±11.5
±11.5
±11.5
±12
Minimum
V
DD
/V
CC
SS
supply
(V)
Rev. PrD | Page 10 of 16
up the REFSEL pin must be tied to either a high or low logic
state to select either the internal or external reference option. If
the internal reference is the preferred option, the user must tie
the REFSEL pin logic high. Alternatively, if REFSEL is tied to
GND then an external reference can be supplied to both ADC’s
through D
The analog inputs are configured as two single ended inputs for
each ADC. The various different input voltage ranges can be
selected by programming the RANGE bits as shown in Table 7.
The AD7367 also features power-down option to allow power
saving between conversions. The power-down feature is
implemented via the
Operation section.
Converter Operation
The AD7367 has two successive approximation analog-to-
digital converters, each based around two capacitive DACs.
Figure 3 and Figure 4 show simplified schematics of one of
these ADCs in acquisition and conversion phase, respectively.
The ADC is comprised of control logic, a SAR, and two
capacitive DACs. In Figure 3 (the acquisition phase), SW2 is
closed and SW1 is in Position A, the comparator is held in a
balanced condition, and the sampling capacitor arrays acquire
the signal on the input.
When the ADC starts a conversion (Figure 4), SW2 opens and
SW1 moves to Position B, causing the comparator to become
unbalanced. The control logic and the charge redistribution
DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code.
AGND
V
IN
CAP
A & D
SW1
A
Figure 3 ADC Acquisition Phase
CAP
Preliminary Technical Data
B
CONVST
B pins.
SW2
pin as described in the Modes of
COMPARATOR
CAPACITIVE
CONTROL
LOGIC
DAC