AD7367-5ARUZ-REEL7 AD [Analog Devices], AD7367-5ARUZ-REEL7 Datasheet - Page 15

• Manufacturer Part Number: AD7367-5ARUZ-REEL7
• Description: True Bipolar Input, Dual 1us, 14-Bit, 2-Channel SAR ADC
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
Figure 9 shows the detailed timing diagram for serial inter-
facing to the AD7367. On the falling edge of CONVST the
AD7367 will simultaneously convert the selected channels.
These conversions are performed using the on-chip oscillator.
After the falling edge of CONVST the BUSY signal goes high,
indicating the conversion has started. It returns low once the
conversion has been completed. The data can now be read from
the
AD7367. The AD7367 has two output pins corresponding to
each ADC. Data can be read from the AD7367 using both
D
choice can be used. The SCLK input signal provides the
clock source for the serial interface. The CS goes low to
access data from the AD7367. The falling edge of CS takes
the bus out of three-state and clocks out the MSB of the
conversion result. The data stream consists of 14 bits of data
MSB first. The first bit of the conversion result is valid on the
first SCLK falling edge after the CS falling edge. The
subsequent 13 bits of data are clocked out on the falling edge
of the SCLK signal. A minimum of 14 Clock pulses must be
SERIAL INTERFACE
D
CS and SCLK signals are required to transfer data from the
SCLK
OUT
D OUT A
D OUT B 3-STATE
OUT
CS
D
SCLK
A
CS
A & D
OUT
THREE-
STATE
pins.
OUT
DB13
B, alternatively a single output pin of your
1
A
DB12
DB13
t
4
t
1
A
4
DB12
2
DB11
A
2
3
DB11
Figure 10. Reading Data from Both ADC’s on ONE D
3
4
DB10
t
t
8
5
t
5
7
4
Figure 9. Serial Interface Timing diagram
t
5
t
8
12
DB1
Rev. PrD | Page 15 of 16
5
t
6
A
t
13
6
DB0
A
provided to AD7367 to access each conversion result.
9
results.
On the rising edge of CS , the conversion will be terminated
and D
brought high, but is instead held low for a further 14 SCLK
cycles on either D
ADC follows on the D
where the case for D
line in use goes back into three-state on the rising edge of CS
If the falling edge of SCLK coincides with the falling edge of
CS , then the falling edge of SCLK is not acknowledged by
the AD7367, and the next falling edge of the SCLK will be
the first registered after the falling edges of the CS .
The CS pin can be brought low before the BUSY signal goes
low indicating the end of a conversion. This feature can be
utilized to ensure that the MSB is valid on the falling edge of
BUSY by bring CS low a minimum of t
BUSY signal goes low. The dotted
this.
14
DB13
shows how a 14 SCLK read is used to access the conversion
B
OUT
DB2
OUT
15
DB12
A and D
Line with 28 SCLK’s
B
t
7
DB1
OUT
OUT
OUT
B go back into three-state. If CS is not
A or D
OUT
A is shown. In this case, the D
DB0
pin. This is illustrated in
t
9
OUT
B, the data from the other
14
DB1
CS line
B
3-STATE
4
nanoseconds before the
in Table 7 illustrates
DB0
B
28
t
10
AD7367
Figure 10
THREE-
STATE
OUT
Figure