AD7367-5ARUZ-REEL7 AD [Analog Devices], AD7367-5ARUZ-REEL7 Datasheet - Page 5

• Manufacturer Part Number: AD7367-5ARUZ-REEL7
• Description: True Bipolar Input, Dual 1us, 14-Bit, 2-Channel SAR ADC
• Manufacturer: AD [Analog Devices]

AD7367
TIMING SPECIFICATIONS
AV
otherwise noted
Table 3.
Parameter
t
f
t
t
t
t
t
t
t
t
t
t
t
t
1
2
SCLK
CONVERT
QUIET
1
2
3
4
5
6
7
8
9
10
POWER-UP
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See
Terminology section and Figure 9.
The time required for the output to cross 0.4 V or 2.4 V.
2
CC
= DV
CC
=4.75 V to 5.25 V, V
2.7V≤V
680
10
30
10
5
0
10
20
5
0.1 t
0.1 t
10
5
10
70
35
1
.
SCLK
SCLK
DRIVE
Limit at T
<4.75V
DD
MIN
4.75V≤V
680
10
48
30
10
5
0
10
14
5
0.1 t
0.1 t
10
5
10
70
= 11.5V to 16.5 V, V
, T
SCLK
SCLK
MAX
DRIVE
≤5.25V
Unit
ns max
kHz min
MHz
max
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns max
μs
SS
= −11.5V to −16.5 V, V
Rev. PrD | Page 5 of 16
Test Conditions / Comments
Conversion time, Internal clock. CONVST falling edge to BUSY falling
edge
Frequency of serial read clock.
Minimum quiet time required between end of serial read and start of
next conversion
Minimum CONVST Low pulse.
CONVST falling edge to BUSY rising edge.
BUSY falling edge to MSB valid once CS is low for t
Low
Delay from CS falling edge until DOUTA and DOUTB are three-state
disabled
Data access time after SCLK falling edge
SCLK low pulse width
Power up time from shutdown mode. Time required between CONVST
rising edge and CONVST falling edge.
SCLK to data valid hold time
SCLK high pulse width
SCLK falling edge to DOUTA, DOUTB, high impedance
SCLK falling edge to DOUTA, DOUTB, high impedance
CS rising edge to DOUTA, DOUTB, high impedance
DRIVE
= 2.7 V to 5.25V, T
Preliminary Technical Data
DD
) and timed from a voltage level of 1.6 V.
A
= T
MIN
to T
4
prior to BUSY going
MAX
, unless