AD7367-5ARUZ-REEL7 AD [Analog Devices], AD7367-5ARUZ-REEL7 Datasheet - Page 13

• Manufacturer Part Number: AD7367-5ARUZ-REEL7
• Description: True Bipolar Input, Dual 1us, 14-Bit, 2-Channel SAR ADC
• Manufacturer: AD [Analog Devices]

AD7367
MODES OF OPERATION
The mode of operation of the AD7367 is selected by the (logic) state of the CONVST signal at the end of a conversion. There are two
possible modes of operation: normal mode and shut-down mode. These modes of operation are designed to provide flexible power
management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for differing application
requirements.
NORMAL MODE
This mode is intended for applications needing fast throughput
rates since the user does not have to worry about any power-up
times with the AD7367 remaining fully powered at all times.
Figure 7 shows the general mode of operation of the AD7367 in
this mode.
The conversion is initiated on the falling edge of CONVST as
described in the Circuit Information section. To ensure that the
part remains fully powered up at all times, CONVST must be at
logic state high prior to the BUSY signal going low. If CONVST
is at logic state low when the BUSY signal goes low, the
analogue circuitry will power down and the part will cease
converting. The BUSY signal remain high for the duration of
the conversion subsequently fourteen serial clock cycles are
required to read the conversion result. The D
three-state when CS is brought high and not after 14 SCLK
cycles has elapsed. If CS is left low for a further 14 SCLK cycles,
SHUT-DOWN MODE
This mode is intended for use in applications where slow
throughput rates are required. This mode is suited to
applications where a series of conversions performed at a
relatively high throughput rate are followed by a long period of
inactivity and thus, shut-down. When the AD7367 is in full
power-down, all analog circuitry is powered down. As already
stated, the falling edge of CONVST initiates the conversion.
The BUSY output subsequently goes high to indicate that the
conversion is in progress. Once the conversion is completed, the
BUSY output returns low. If the CONVST signal is at logic low
CONVST
BUSY
SCLK
CS
t 2
SERIAL READ OPERATION
t 1
OUT
lines return to
t convert
Figure 7. Normal Mode Operation
Rev. PrD | Page 13 of 16
t
1
3
the result from the other on chip ADC is also accessed on the
same D
section)
Once 28 SCLK cycles have elapsed, the D
three-state when CS is brought high and not on the 28
falling edge. If CS is brought high prior to this, the D
returns to three-state at that point. Thus, CS must be brought
high once the read is completed, as the bus does not
automatically return to three-state upon completion of the dual
result read.
Once a data transfer is complete and D
returned to three-state, another conversion can be initiated after
the quiet time, t
again.
when BUSY goes low then the part will enter shut-down at the
end of the conversion phase. While the part is in shut-down
mode the digital output code from the last conversion on each
ADC can still be read from the D
CS
Section. The D
back to logic high.
To exit full power-down and power up the AD7367, A rising
edge of CONVST is required. After the required power up time
has elapsed, CONVST may be brought low again to initiate
must be brought low as described in the Serial Interface
OUT
line, as shown in
OUT
QUIET
pins return to three-state once
Preliminary Technical Data
, has elapsed by bringing CONVST low
t quiet
14
Figure 10
OUT
pins. To read the D
(see the Serial Interface
OUT
OUT
A and D
line returns to
CS
OUT
OUT
is brought
B have
th
OUT
SCLK
line
data