DAC1408D650HN NXP [NXP Semiconductors], DAC1408D650HN Datasheet - Page 25

• Manufacturer Part Number: DAC1408D650HN
• Description: Dual 14-bit DAC; up to 650 Msps; 2?, 4? or 8? interpolating with JESD204A interface
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1408D650
Product data sheet
10.4 Clock input
The DAC1408D650 has one differential clock input, CLKINN/CLKINP.
The DAC1408D650 can operate with a clock frequency up to 312.5 MHz or up to
650 MHz if the internal PLL is bypassed. The clock input can be LVDS (see
it can also be interfaced with CML (see
internal clock domain to another one is handled by Clock Domain Interface logic.
During the reset phase (RESET_N asserted), the clock must be stable and running. This
ensures a proper reset of the complete device.
The device has no embedded power-on-reset feature. Driving the RESET_N pin to set the
device to its default state is mandatory.
Fig 15. LVDS clock configuration
Fig 16. Interfacing CML to LVDS
All information provided in this document is subject to legal disclaimers.
CML
Rev. 4 — 26 November 2010
Z
LVDS
diff = 100 Ω
Z
diff
= 100 Ω
1 kΩ
100 nF
100 nF
Figure
2, 4 or 8 interpolating DAC with JESD204A
V
DDA(1V8)
AGND
CLKINP
CLKINN
100 Ω
1.1 kΩ
2.2 kΩ
16). Error free data transition from one
55 Ω
55 Ω
CLKINN
CLKINP
100 nF
001aah021
DAC1408D650
LVDS
001aah020
LVDS
© NXP B.V. 2010. All rights reserved.
Figure
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