DSP56011 MOTOROLA [Motorola, Inc], DSP56011 Datasheet
DSP56011
Related parts for DSP56011
DSP56011 Summary of contents
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... Motorola’s 24-bit DSP56000 architecture and are the highest quality solutions available. Flexible peripheral modules and interface software allow simple connection to a wide variety of video/ system decoders. In addition, the DSP56011 offers switchable memory space configuration, a large user-definable Program ROM and two independent data RAMs and ROMs, a Serial Audio ...
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... Examples: Signal/Symbol PIN PIN PIN PIN Note: Values for and DSP56011 Technical Data Sheet, Rev. 1 TABLE OF CONTENTS 1-800-521-6274 dsphelp@dsp.sps.mot.com http://www.motorola-dsp.com Logic State Signal State True Asserted False Deasserted True Asserted False Deasserted are defined by individual product specifications. ...
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... Four 24-bit internal data buses and three 16-bit internal address buses for simultaneous accesses to one program and two data memories MOTOROLA DSP56011 Technical Data Sheet, Rev 15), which reduces clock noise Preliminary Information DSP56011 ...
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... Program RAM and 64 24-bit bootstrap ROM • As much as 2304 24 bits of X- and Y-data RAM can be switched to Program RAM, giving a total of 2816 24 bits of Program RAM Table 1 lists the memory configurations of the DSP56011. Table 1 DSP56011 Internal Memory Configurations No Switch ...
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... Power saving Wait and Stop modes • Fully static, HCMOS design from specified operating frequency down to dc • 100-pin plastic Thin Quad Flat Pack (TQFP) surface-mount package • power supply MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 Preliminary Information DSP56011 Features v ...
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... DSP56011 Documentation DOCUMENTATION Table 2 lists the documents that provide a complete description of the DSP56011 and are required to design properly with the part. Documentation is available from a local Motorola distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or through the Motorola DSP home page on the Internet (the source for the latest information). ...
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... SIGNAL/CONNECTION DESCRIPTIONS SIGNAL GROUPINGS The input and output signals of the DSP56011 are organized into ten functional groups, as shown in Table 1-1 and as illustrated in Figure 1-1 . Table 1-1 DSP56011 Functional Signal Groupings Functional Group Power ( Ground (GND) PLL Interrupt and Mode Control Host Interface (HI) ...
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... GND SHI S PLOCK PLL PCAP PINIT EXTAL MODA/IRQA Interrupt/ MODB/IRQB Mode MODC/NMI Control RESET Figure 1-1 Signals Identified by Functional Group 1-2 DSP56011 Technical Data Sheet, Rev. 1 DSP56011 HI 8 Host H0–H7 Interface HOA0 (HI) Port HOA1 HOA2 HR/W HEN HOREQ HACK SPI Mode MOSI Serial Host ...
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... Serial Host Power—V CCS input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 Table 1-2 Power Inputs Description is V dedicated for Phase Lock Loop (PLL) use. The voltage ...
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... Serial Host Ground—GND S connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. 1-4 DSP56011 Technical Data Sheet, Rev. 1 Table 1-3 Grounds Description is ground dedicated for PLL use. The connection should 0.1 F capacitor located as close as possible to the chip ...
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... Input Input EXTAL Input Input MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 Table 1-4 Phase Lock Loop Signals Signal Description Reset Phase Locked—PLOCK is an output signal that, when driven high, indicates that the PLL has achieved phase lock. After Reset, PLOCK is driven low until lock is achieved ...
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... MODA Input Input (MODA) Mode Select A—This input signal has three functions: IRQA Input 1-6 DSP56011 Technical Data Sheet, Rev. 1 Signal Description • to work with the MODB and MODC signals to select the DSP’s initial operating mode, • to allow an external device to request a DSP interrupt after internal synchronization, and • ...
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... MODB Input Input (MODB) Mode Select B—This input signal has two functions: IRQB Input MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 Signal Description • to work with the MODA and MODC signals to select the DSP’s initial operating mode, and • to allow an external device to request a DSP interrupt after internal synchronization ...
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... NMI Input, edge- triggered RESET Input Active 1-8 DSP56011 Technical Data Sheet, Rev. 1 Signal Description • to work with the MODA and MODB signals to select the DSP’s initial operating mode, and • to allow an external device to request a DSP interrupt after internal synchronization. ...
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... HEN is deasserted. The signals are inputs unless HR/W is high and HEN is asserted, in which case H0–H7 become outputs, allowing the host processor to read the DSP56011 data. H0–H7 become outputs when HACK is asserted during HOREQ assertion. Port B GPIO 0–7 (PB0–PB7)—These signals are General Purpose I/O signals (PB0– ...
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... When HEN is asserted and HR/W is high, H0–H7 become outputs and the host processor may read DSP56011 data. When HEN is asserted and HR/W is low, H0–H7 become inputs. Host data is latched inside the DSP on the rising edge of HEN. Normally, a chip select signal derived from host address decoding and an enable strobe are used to generate HEN ...
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... HACK Input Input PB14 Input/ Output MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 Signal Description Reset Host Acknowledge—This input has two functions. It provides a host acknowledge handshake signal for DMA transfers and it receives a host interrupt acknowledge compatible with MC68000 Family processors. Note: HACK should always be pulled high when it is not in use ...
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... Output SCL Input or Output 1-12 DSP56011 Technical Data Sheet, Rev. 1 Signal Description SPI Serial Clock—The SCK signal is an output when the SPI is configured as a master, and a Schmitt-trigger input when the SPI is configured as a slave. When the SPI is configured as a master, the SCK signal is derived from the internal SHI clock generator ...
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... Tri-stated Output HA0 Input MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 Signal Description SPI Master-In-Slave-Out—When the SPI is configured as a master, MISO is the master data input line. The MISO signal is used in conjunction with the MOSI signal for transmitting and receiving serial data. This signal is a Schmitt-trigger ...
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... HREQ Input or Tri-stated Output 1-14 DSP56011 Technical Data Sheet, Rev. 1 Signal Description SPI Slave Select—This signal is an active low Schmitt-trigger input when configured for the SPI mode. When configured for the SPI Slave mode, this signal is used to enable the SPI slave for transfer. When configured for the SPI Master mode, this signal should be kept deasserted (pulled high) ...
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... Input or Tri- Output stated MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 Signal Description Serial Data Input 0—This is the receiver 0 serial data input. This signal is high impedance during hardware or software reset, while receiver 0 is disabled (R0EN = 0), or while the chip is in the Stop state. No external pull-up resistor is required. ...
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... Input Tri- or stated Output 1-16 DSP56011 Technical Data Sheet, Rev. 1 Signal Description Serial Data Output 0—SDO0 is the transmitter 0 serial output. SDO0 is driven high if transmitter 0 is disabled, during personal reset, hardware reset and software reset, or when the chip is in the Stop state. Serial Data Output 1—SDO1 is the transmitter 1 serial output. ...
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... Table 1-11 Digital Audio Interface (DAX) Signals Signal Name Type ADO Output ACI Input MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 General Purpose Input/Output (GPIO) State during Reset Disconnected General Purpose Input/Output—These signals internally are used for control and handshake functions between the DSP and external circuitry. Each ...
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... Low Output OS1 Output 1-18 DSP56011 Technical Data Sheet, Rev. 1 Signal Description Debug Serial Input—In Debug mode, serial data or commands are provided as inputs to the OnCE controller via the DSI signal. Data is latched on the falling edge of the DSCK serial clock. Data is always shifted into the OnCE serial port Most Significant Bit (MSB) first ...
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... DR Input Input MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 Signal Description Debug Serial Output—Data contained in one of the OnCE controller registers is provided through the DSO output signal, as specified by the last command received from the external command controller. Data is always shifted out the OnCE serial port MSB first ...
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... Signal/Connection Descriptions OnCE Port 1-20 DSP56011 Technical Data Sheet, Rev. 1 Preliminary Information MOTOROLA ...
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... INTRODUCTION The DSP56011 is fabricated in high density CMOS with Transistor-Transistor Logic (TTL) compatible inputs and outputs. The DSP56011 specifications are preliminary and are from design simulations, and may not be fully tested or guaranteed at this early stage of the product life cycle. For design convenience, timings for 81 MHz and 95 MHz operation are included ...
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... Measurements were done with parts mounted on thermal test boards conforming to specification EIA/JESD51-3. 2. Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30- 88, with the exception that the cold plate temperature is used for the case temperature. 2-2 DSP56011 Technical Data Sheet, Rev. 1 Table 2-1 Maximum Ratings Symbol ...
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... In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). PLL signals are disabled during Stop state. 3. Periodically sampled and not 100% tested 4. Maximum values can be derived using the methodology described in Section 4. Actual maximums are application dependent and may vary widely. MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 Symbol Min V 4. 4.0 ...
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... MISO/SDA, SCK/SCL, HREQ). These inputs are tested using the input levels set forth in the DC Electrical Characteristics. AC timing specifications that are referenced to a device input signal are measured in production with respect to the 50% point of the respective input signal’s transition. DSP56011 output levels are measured with the production test machine V 0.8 V and 2.0 V, respectively. ...
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... EXTERNAL CLOCK OPERATION The DSP56011 system clock is externally supplied via the EXTAL pin. Timings shown in this document are valid for clock rise and fall times maximum. The 81 MHz speed allows the DSP56011 to take advantage of the 27 MHz system clock in DVD applications. No. ...
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... Minimum edge-triggered interrupt request assertion width 16a Minimum edge-triggered interrupt request deassertation width 18 Delay from IRQA, IRQB, NMI assertion to GPIO valid caused by first interrupt instruction execution • GPIO0–GPIO7 • PB0–PB14 2-6 DSP56011 Technical Data Sheet, Rev. 1 Expression PCAP @ > ...
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... When using fast interrupts and IRQA and IRQB are defined as level-sensitive, timing 22 applies to prevent multiple interrupt service. To avoid these timing restrictions, negative-edge-triggered configuration is recommended when using fast interrupts. Long interrupts are recommended when using level-sensitive configuration. RESET MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 RESET, Stop, Mode Select, and Interrupt Timing Min ...
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... IRQA IRQB NMI Figure 2-5 External Level-Sensitive Fast Interrupt Timing 25 IRQA Figure 2-6 Recovery from Stop State Using IRQA IRQA Figure 2-7 Recovery from Stop State Using IRQA Interrupt Service 2-8 DSP56011 Technical Data Sheet, Rev IHM V ILM 16 16A 22 General Purpose I/O 27 Preliminary Information ...
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... HOA0–HOA2 Hold Time After HEN Deassertion 45 DMA HACK assertion to HOREQ deassertion 46 DMA HACK deassertion to HOREQ assertion • For DMA RXL read • For DMA TXL write • All other cases MOTOROLA DSP56011 Technical Data Sheet, Rev 4,5 T Preliminary Information ...
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... Specifications are periodically sampled and not 100% tested. 6. May decrease for future versions HOREQ (Output) HACK (Input) 41 HR/W (Input) 35 H0–H7 (Output) Figure 2-8 Host Interrupt Vector Register (IVR) Read 2-10 DSP56011 Technical Data Sheet, Rev Data Valid Preliminary Information Min Max Unit ...
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... TXH HEN Write (Input HA2–HA0 Address Valid (Input) 39 HR/W (Input) 33 H0–H7 (Output) Figure 2-10 Host Write Cycle (Non-DMA Mode) MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 RXM Read 32 44 Address Valid Data Valid TXM Write 32 44 Address Valid 40 34 ...
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... H0–H7 Valid (Output) HOREQ (Output TXH HACK Write (Input) 33 H0–H7 Data (Output) Valid 2-12 DSP56011 Technical Data Sheet, Rev RXM Read 37 38 Data Valid Figure 2-11 Host DMA Read Cycle 46 32 TXM Write 34 Data Valid Figure 2-12 Host DMA Write Cycle ...
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... Notes: 1. When the Frequency Ratio between Parallel and Serial clocks is 1:4 or greater 2. When the Frequency Ratio between Parallel and Serial clocks is 1:3 – 1:4 MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 Serial Audio Interface (SAI) Timing) Mode Expression Master 4 T ...
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... Specifications Serial Audio Interface (SAI) Timing) SCKR (RCKP = 1) SCKR (RCKP = 0) SDI0–SDI1 (Data Input) WSR (Input) WSR (Output) 2-14 DSP56011 Technical Data Sheet, Rev. 1 111 112 114 111 113 114 115 116 Valid 119 118 Valid Figure 2-13 SAI Receiver Timing Preliminary Information ...
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... SCKT (TCKP = 1) SCKT (TCKP = 0) SDO0–SDO2) (Data Output) WST (Input) WST (Output) MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 111 112 114 111 113 114 121 124 123 Valid Figure 2-14 SAI Transmitter Timing Preliminary Information Specifications Serial Audio Interface (SAI) Timing) 114 ...
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... Frequency above 1 33 MHz 2 CPHA = 0, CPHA = 1 CPHA = 1 142 Serial Clock high period 2 CPHA = 0, CPHA = 1 CPHA = 1 143 Serial Clock low period 2 CPHA = 0, CPHA = 1 CPHA = 1 2-16 DSP56011 Technical Data Sheet, Rev. 1 Filter Mode Expression Mode Bypassed Narrow Wide Master Bypassed Master Bypassed 6 ...
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... Data input valid to SCK edge (data input setup time) 149 SCK edge to data input not valid (data in hold time) 150 SS assertion to data out active MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 Serial Host Interface (SHI) SPI Protocol Timing Filter Mode Expression Mode Master 10 Slave ...
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... CPHA = 0 157 First SCK sampling edge to HREQ output deassertation 158 Last SCK sampling edge to HREQ output not deasserted CPHA = 1 159 SS deassertion to HREQ output not deasserted CPHA = 0 2-18 DSP56011 Technical Data Sheet, Rev. 1 Filter Mode Expression Mode Slave 24 Master Bypassed 41 Narrow 214 Wide ...
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... T the first edge of SCK of each word. 3. When CPHA = 1, the SS line may remain active low between successive transfers. 4. Periodically sampled, not 100% tested MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 Serial Host Interface (SHI) SPI Protocol Timing Filter Mode Expression Mode Slave ...
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... SCK (CPOL = 0) (Output) SCK (CPOL = 1) (Output) 148 MISO (Input) MOSI (Output) 161 HREQ (Input) Figure 2-15 SPI Master Timing (CPHA = 0) 2-20 DSP56011 Technical Data Sheet, Rev. 1 143 144 142 144 143 148 149 MSB Valid 152 MSB 163 Preliminary Information 141 144 ...
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... SCK (CPOL = 0) (Output) SCK (CPOL = 1) (Output) MISO (Input) MOSI (Output) 161 HREQ (Input) Figure 2-16 SPI Master Timing (CPHA = 1) MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 Serial Host Interface (SHI) SPI Protocol Timing 143 144 142 144 143 148 149 MSB Valid 152 MSB ...
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... SCK (CPOL = 0) (Input) 146 SCK (CPOL = 1) (Input) 154 150 MISO (Output) 148 MOSI (Input) HREQ (Output) Figure 2-17 SPI Slave Timing (CPHA = 0) 2-22 DSP56011 Technical Data Sheet, Rev. 1 143 142 144 142 144 143 152 153 153 MSB 148 149 MSB Valid 157 ...
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... SCK (CPOL = 1) (Input) 152 150 MISO (Output) MOSI (Input) HREQ (Output) Figure 2-18 SPI Slave Timing (CPHA = 1) MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 Serial Host Interface (SHI) SPI Protocol Timing 143 144 142 144 143 152 MSB 148 149 MSB Valid ...
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... SCL and SDA fall time 179 Data setup time 180 Data hold time 182 SCL low to data output valid 183 Stop condition setup time 2-24 DSP56011 Technical Data Sheet, Rev PROTOCOL TIMING 2 C Protocol Timing 2 Standard 400 pF 100 kHz) ...
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... The actual maximum frequency is limited by the bus capacitances (C up resistors (R ), (which affect the rise and fall time of SDA and SCL, see Table 2- page 2-26), and by the input filters. MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 Serial Host Interface (SHI) I2C Protocol Timing , is specified by the value of the HDM5– CCP ...
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... MHz Example: for pF when operating with a DSP56011 SHI I must generate a bus free time greater than 36 ns (T172 slave). Thus, the minimum permissible CCP master). This implies a maximum I In general, bus performance may be calculated from the C the input filter modes and operating frequencies of the master and the slave. ...
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... Bus free time T BUF 173 Start condition T SU;STA setup time 174 Start condition T HD;STA hold time MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 Serial Host Interface (SHI) I2C Protocol Timing 2 C Protocol Timing 2 Improved pF Filter Mode ...
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... T R Output Input 178 SCL fall time T F Output Input 179 Data setup time T SU;DAT 180 Data hold time T HD;DAT 2-28 DSP56011 Technical Data Sheet, Rev Protocol Timing (Continued) 2 Improved pF Filter Mode Expression Mode Master Bypassed 0 – ...
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... HREQ input assertion to first SCL edge 189 First SCL edge to HREQ input not asserted (HREQ input hold time) MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 Serial Host Interface (SHI) I2C Protocol Timing 2 C Protocol Timing (Continued) 2 Improved pF ...
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... Narrow filter mode load) was used for the calculations in the Wide filter mode. 173 176 SCL 177 172 SDA Stop Start 174 188 HREQ 2-30 DSP56011 Technical Data Sheet, Rev Protocol Timing (Continued) 2 Improved pF Filter Mode Expression Mode ...
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... PB0–PB14 (Output) GPIO0–GPIO7 PB0–PB14 (Input) Note: Valid when the ratio between EXTAL frequency and internal clock frequency equals 1 MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 General Purpose Input/Output (GPIO) Timing Table 2-14 GPIO Timing Expression 203 204 Valid Figure 2-20 GPIO Timing ...
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... ACI Rising Edge to ADO Valid Note: In order to assure proper operation of the DAX, the ACI frequency should be less than 1/2 of the DSP56011 internal clock frequency. For example, if the DSP56011 is running at 40 MHz internally, the ACI frequency should be less than 20 MHz. ACI 223 ...
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... To recover from Wait • To recover from Wait and enter Debug mode 249 DR assertion to DSO (ACK) valid (enter Debug mode) after asynchronous recovery from Wait state MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 On-Chip Emulation (OnCE ) Timing Table 2-16 OnCE Timing All Frequencies Min 40 40 200 — ...
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... Stable External Clock, OMR Bit • Stable External Clock, PCTL Bit 17= 1 Notes: 1. Maximum Periodically sampled, not 100% tested DSCK (input) Figure 2-22 DSP56011 OnCE Serial Clock Timing DR (Input) DSO (Output) Figure 2-23 DSP56011 OnCE Acknowledge Timing 2-34 DSP56011 Technical Data Sheet, Rev. 1 All Frequencies Min 2 ...
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... DSCK (Input) DSO (Output) 236 DSI (Input) Note: High Impedance, external pull-down resistor Figure 2-24 DSP56011 OnCE Data I/O to Status Timing DSCK (Input) 234 DSO (Output) Note: High Impedance, external pull-down resistor Figure 2-25 DSP56011 OnCE Read Timing OS1 (Output) 241 DSO (Output) OS0 ...
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... Note: 1. High Impedance, external pull-down resistor 2. Valid when the ratio between EXTAL frequency and clock frequency equals 1 Figure 2-27 DSP56011 OnCE EXTAL to Status Timing DSCK (Input) Figure 2-28 DSP56011 OnCE DSCK Next Command After Read Register Timing EXTAL DR (Input) DSO (Output) Figure 2-29 Synchronous Recovery from Wait State ...
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... DR (Input) DSO (Output) Figure 2-31 Asynchronous Recovery from Stop State MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 On-Chip Emulation (OnCE ) Timing 250 251 Preliminary Information Specifications AA0286 2-37 ...
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... Specifications On-Chip Emulation (OnCE ) Timing 2-38 DSP56011 Technical Data Sheet, Rev. 1 Preliminary Information MOTOROLA ...
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... PIN-OUT AND PACKAGE INFORMATION This sections provides information about the available packages for this product, including diagrams of the package pinouts and tables describing how the signals described in Section 1 are allocated. The DSP56011 is available in a 100-pin Thin Quad Flat Pack (TQFP) package. MOTOROLA DSP56011 Technical Data Sheet, Rev ...
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... CCA Orientation Mark not connected not connected GND A not connected not connected not connected V 100 CCA Figure 3-1 DSP56011 Thin Quad Flat Pack (TQFP), Top View 3-2 DSP56011 Technical Data Sheet, Rev. 1 (Top View) Preliminary Information 50 V CCS MODC/NMI MODB/IRQB MODA/IRQA RESET MISO/SDA ...
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... ACI ADO V CCH GND H HOREQ/PB13 H0/PB0 26 Figure 3-2 DSP56011 Thin Quad Flat Pack (TQFP), Bottom View MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 Orientation Mark (Bottom View) Preliminary Information Packaging Pin-out and Package Information GPIO7 76 GPIO6 GND ...
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... H5/PB5 CCH 21 H4/PB4 46 22 H3/PB3 47 23 GND H2/PB2 49 25 H1/PB1 50 3-4 DSP56011 Technical Data Sheet, Rev. 1 Table 3-1 Signal by Pin Number Signal Name Pin # Signal Name H0/PB0 51 MOSI/HA0 HOREQ/ 52 SS/HA2 PB13 GND 53 HREQ GND CCH ADO 55 SDO2 ACI 56 ...
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... MODC GPIO1 85 GPIO2 83 GPIO3 82 not connected GPIO4 80 not connected GPIO5 79 not connected GPIO6 77 not connected MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 Table 3-2 Signal by Name Pin # Signal Name 76 not connected H0 26 not connected H1 25 not connected H2 24 not connected H3 22 not connected ...
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... Pin-out and Package Information 0 100 1 L VIEW 0. Figure 3-3 100-pin Thin Quad Flat Pack (TQFP) Mechanical Information 3-6 DSP56011 Technical Data Sheet, Rev. 1 0 TIPS 0.08 T SEATING PLANE 3 4X VIEW AA (W) ...
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... Specific part technical information or data sheets – Other information described by the system messages A total of three documents may be ordered per call. The DSP56011 100-pin TQFP package mechanical drawing is referenced as 983-02. MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 (602) 244-6609 Preliminary Information Packaging ...
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... Packaging Ordering Drawings 3-8 DSP56011 Technical Data Sheet, Rev. 1 Preliminary Information MOTOROLA ...
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... For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the printed circuit board, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 SECTION + P R ...
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... The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. 4-2 DSP56011 Technical Data Sheet, Rev not satisfactorily answer whether the thermal determined by a thermocouple, T ...
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... All inputs must be terminated (i.e., not allowed to float) using CMOS levels, except as noted in Section 1. • Take special care to minimize noise levels on the V • If multiple DSP56011 devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices. MOTOROLA DSP56011 Technical Data Sheet, Rev ...
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... Minimize the number of pins that are switching. • Minimize the capacitive load on the pins. • Connect the unused inputs to pull-up or pull-down resistors. • Disable unused peripherals. • Disable unused pin activity. 4-4 DSP56011 Technical Data Sheet, Rev. 1 Example 4-1 Current Consumption – ...
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... TP1 nop jmp MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 Power Consumption Considerations MAIN p:MAIN #$180000,x:$FFFD #0,r0 #0,r4 #0,r5 #$00FF,m0 #$00FF,m4 #256 r0,x:(r0)+ #256 r4,y:(r4)+ a l:(r0)+,a #30 x0,y0,a x:(r0)+,x0 a,p:(r5) TP1 MAIN ...
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... At the beginning of the hardware reset procedure, the device might consume significantly more current than the specified typical supply current. This is because of contentions among the internal nodes being affected by the hardware reset signal until they reach their final hardware reset state. 4-6 DSP56011 Technical Data Sheet, Rev. 1 Preliminary Information MOTOROLA ...
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... DSP. Because the host does not know exactly when the exception will be recognized (due to exception processing synchronization and pipeline delays), the DSP may execute the host MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 Preliminary Information Design Considerations Host Port Considerations ...
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... HF0 and HF1 as an encoded pair, (i.e., the four combinations 00, 01, 10, and 11 each have significance). A very small probability exists that the DSP will read the status bits synchronized during transition. Therefore, HF0 and HF1 should be read twice and checked for consensus. 4-8 DSP56011 Technical Data Sheet, Rev. 1 Preliminary Information MOTOROLA ...
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... The DSPA56011 and the DSPB56011 include factory-programmed ROM containing support for Dolby AC- 3 with DVD specifications. These parts can be used only be customers licensed for Dolby AC-3. Future products in the DSP56011 family will include other ROM-based options. For additional information on future part development request customer-specific ROM-based support, call your local Motorola Semiconductor sales office or authorized distributor ...
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OnCE, Mfax, and Symphony are trademarks of Motorola, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, ...