DSP56156FV40 MOTOROLA [Motorola, Inc], DSP56156FV40 Datasheet
DSP56156FV40
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DSP56156FV40 Summary of contents
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Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA Advance Information 16-bit Digital Signal Processor The DSP56156 is a general-purpose MPU-style Digital Signal Processor (DSP single semi- conductor chip, the DSP56156 comprises a very efficient 16-bit digital signal processing core, ...
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Introduction DSP56156 Features DSP56156 Features Digital Signal Processing Core • Efficient, object code compatible, 16-bit 56100-Family DSP engine — Million Instructions Per Second (MIPS) – instruction cycle at 60 MHz — 180 Million ...
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Freescale Semiconductor, Inc. • On-chip peripheral registers memory mapped in data memory space • Double buffered peripherals • general purpose I/O pins • Two external interrupt request pins • On-Chip Emulation (OnCE™) port for unobtrusive, processor speed-independent ...
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Introduction Documentation Data Sheet Contents Related Documentation Table 2 lists additional documentation relevant to the DSP56156. Table 2 Related Motorola Documentation Topic DSP Family Brochure Development Tools Fractional and Integer Arithmetic Fast Fourier Transforms (FFTs) G.722 Audio Processing Dr. BuB ...
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Freescale Semiconductor, Inc. Pin Groupings The DSP56156 is available in a 112-pin Ceramic Quad Flat Pack (CQFP) and a 112-pin Plastic Thin Quad Flat Pack (TQFP). The input and output signals are organized into the functional groups indicated in Table ...
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Introduction Pin Functions A0-A15 D0-D15 PS/DS R/W BB MODA/IRQA MODB/IRQB MODC RESET DSO DSI/OS0 DSCK/OS1 DR MIC AUX SPKP SPKM BIAS VREF VDIV * These pins have an alternate function of general purpose input/output. ...
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Freescale Semiconductor, Inc. Pin Descriptions Address and Data Bus A0-A15 (Address Bus) — three-state, active high outputs. A0-A15 change in t0 and specify the address for external pro- gram and data memory accesses. If there is no external bus activity, ...
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Pin Descriptions Bus Control TA (Transfer Acknowledge) — active low input. If there is no external bus ac- tivity, the TA input is ignored by the DSP. When there is external bus cycle activity, TA can be used to insert ...
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Freescale Semiconductor, Inc. the BB pin is deasserted. The DSP con- tinues executing instructions only if in- ternal program and data memory resources are accessed. If the DSP re- quests the external bus while BR input pin is asserted, the ...
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Pin Descriptions Bus Control Interrupt and Mode Control BB (Bus Busy) — active low input when not bus master, active low output when bus master. This pin is asserted by the DSP when it becomes the bus master and it ...
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Freescale Semiconductor, Inc. trigger input is used for noise immunity. When the reset pin is deasserted, the ini- tial chip operating mode is latched from the MODA and MODB pins, and the ini- tial bus operating mode is latched from ...
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Pin Descriptions 16-bit Timer SSI acknowledge, HACK enables the HI Interrupt Vector Register (IVR) onto the host data bus H0-H7 if the Host Re- quest HREQ output is asserted. In this case, all other HI control pins are ig- nored ...
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Freescale Semiconductor, Inc. On-Chip Emulation TM (OnCE Port) DSI/OS0 (Debug Serial Input/Chip Status 0) — bidirectional. The DSI/OS0 pin, when an input, is the pin through which seri- al data or commands are provided to the OnCE port controller. The ...
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Pin Descriptions On-Chip Codec Power, Ground, and Clock the codec control register COCR. This pin should be left floating when the co- dec is not used. SPKP (Speaker Plus) — output. This pin is the positive analog output from the ...
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Freescale Semiconductor, Inc. Electrical Characteristics and Timing CAUTION: Exceeding maximum electrical ratings will permanently damage or disable the chip, or impair the chip’s long term reliability. The DSP56156 is fabricated in high density HCMOS with TTL compatible inputs and CMOS ...
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Electrical Characteristics and Timing Analog I/O Characteristics Analog I/O Characteristics ( ± 10 The analog I/O characteristics of this device are listed in Table 7. For additional information regarding the use of analog ...
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Freescale Semiconductor, Inc. A/D and D/A Performance ( ± 10 -40 to +125 C) CCA J The A/D and D/A performance of the codec section are given in Table 8 with an example presented ...
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Electrical Characteristics and Timing Other On-Chip Codec Characteristics Other On-Chip Codec Characteristics ( ± 10%, T CCA The analog I/O characteristics of this device are shown in Table 9. Table 9 Analog I/O Characteristics of On-Chip ...
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Freescale Semiconductor, Inc. DC Electrical Characteristics (GND = ± 10 -40 to +125 The DC electrical characteristics of this device are shown in Table 10. Table ...
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AC Electrical Characteristics and Timing Clock Operation Timing AC Electrical Characteristics (GND = 0 V dc) The timing waveforms in the AC Electrical Characteristics are tested with a V 0.5 V and a V minimum of 2.4 V for all ...
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Freescale Semiconductor, Inc EXTAL 7 4 Figure 5 External Clock Timing Other Clock and PLL Operation Timing Clock and PLL timings are listed in Table 12 and the clocking configurations are illustrated in Figure 6. Table 12 Clock ...
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AC Electrical Characteristics and Timing Reset, Stop, Wait, Mode Select, and Interrupt Timing Reset, Stop, Wait, Mode Select, and Interrupt Timing ( ± 10 cyc = Clock cycle = ws = Number of ...
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Freescale Semiconductor, Inc 5 ± 10 -40 to +125 Table 13 Reset, Stop, Wait, Mode Select, and Interrupt Timing (continued) Num Characteristics 21 Delay from General-Purpose Output Valid Caused by ...
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AC Electrical Characteristics and Timing Reset, Stop, Wait, Mode Select, and Interrupt Timing NOTES: 1. Circuit stabilization delay is required during reset when using an external clock in two cases: • after power-on reset • when recovering from Stop mode ...
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Freescale Semiconductor, Inc. RESET MODA MODB MODC Figure 9 Operating Mode Select Timing IRQA IRQB Figure 10 External Interrupt Timing (Negative Edge-Triggered) A0-A15 PS/DS BS R/W 18 IRQA IRQB a) First Interrupt Instruction Execution General Purpose I/O Pin 19 IRQA ...
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AC Electrical Characteristics and Timing Reset, Stop, Wait, Mode Select, and Interrupt Timing CLKO IRQA IRQB A0-A15 PD/DS BS R/W Figure 12 Synchronous Interrupt from Wait State Timing IRQA A0-A15 PD/DS BS R/W Figure 13 Recovery from Stop State Using ...
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Freescale Semiconductor, Inc. Num Characteristics 30 DR Asserted to CLK high (Setup Time for Synchronous Recovery from Wait State) 31 CLK high to DSO (ACK) Valid (Enter Debug Mode) after Syn- chronous Recovery from Wait State DSO ...
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AC Electrical Characteristics and Timing Reset, Stop, Wait, Mode Select, and Interrupt Timing Capacitance Derating CLKO (output) DR (input) DSO (output) Figure 16 Recovery from Wait/Stop State Using DR Pin — Asynchronous Timing Capacitance Derating The DSP56156 External Bus Timing ...
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Freescale Semiconductor, Inc. External Bus Synchronous Timing ( ± 10 -40 to +125 Table 15 lists external bus synchronous timing. Figure 17 and illustrate the bus timings with no wait ...
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AC Electrical Characteristics and Timing External Bus Synchronous Timing EXTAL (Input) CLKO (Output) A0-A15 PS/DS R/W (See Note) BS (Output) WR (Output) RD (Output) TA (Input) D0-D15 (Output) D0-D15 (Input) NOTE: During Read-Modify-Write instructions and internal instructions, the address lines ...
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Freescale Semiconductor, Inc EXTAL (Input) CLKO 34 (Output) 35 A0-A15, PS/DS, R/W (Outputs (Output (Output (Output (Input) 43 D0-D15 (Output) 50 D0-D15 (Input) Figure 18 External Bus Synchronous Timing – ...
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AC Electrical Characteristics and Timing External Bus Asynchronous Timing External Bus Asynchronous Timing ( ± 10 cyc = Clock cycle = WS = Number of Wait States, Determined by BCR Register ( ...
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Freescale Semiconductor, Inc. A0-A15, PS/DS, R/W (See Note D0-D15 NOTE: During Read-Modify-Write instructions and internal instructions, the address lines do not change state. Figure 19 External Bus Asynchronous Timing MOTOROLA For More Information On ...
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AC Electrical Characteristics and Timing Bus Arbitration Timing — Slave Mode Bus Arbitration Timing — Slave Mode ( ± 10 cyc = Clock cycle = WS = Number of Wait States for external X ...
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Freescale Semiconductor, Inc. CLKO (Output (Input) BG (Output) BB (I/O) A0-A15 PS/DS R/W D0-D15 Figure 20 Bus Arbitration Timing — Slave Mode — Bus Release MOTOROLA For More Information On This Product DSP56156 Data ...
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AC Electrical Characteristics and Timing Bus Arbitration Timing — Slave Mode CLKO (Output (Input) BG (Output) BB (I/O) A0-A15 PS/DS R/W Figure 21 Bus Arbitration Timing — Slave Mode — Bus Acquisition 36 Freescale Semiconductor, Inc ...
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Freescale Semiconductor, Inc. Bus Arbitration Timing — Master Mode ( ± 10 -40 to +125 Num Characteristic 85 CLKO High to BR Output Assertion CLKO High to BR Output Deassertion ...
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AC Electrical Characteristics and Timing Bus Arbitration Timing — Master Mode CLKO (Output) BR (Output (Input) BB (I/O) A0-A15 PS/DS R/W Figure 23 Bus Arbitration Timing — Master Mode — Bus Release 38 Freescale Semiconductor, Inc. 87 DSP56156 ...
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Freescale Semiconductor, Inc. Host Port Timing ( ± 10 -40 to +125 CYC cyc = Clock cycle = t = Host Synchronization Delay Time HSDL ...
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AC Electrical Characteristics and Timing Host Port Timing Table 19 Host Port Timing (continued) Num Characteristic 110 HR/W Low Setup Time before HEN Assertion 111 HR/W Low Hold Time after HEN Deassertion 112 HR/W High Setup Time to HEN Assertion ...
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Freescale Semiconductor, Inc. External Internal Figure 24 Host Synchronization Delay HREQ (Output) HACK (Input) HR/W (Input) 106 H0-H7 (Output) Figure 25 Host Interrupt Vector Register (IVR) Read MOTOROLA For More Information On This Product, 100 100 103 101 113 112 ...
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AC Electrical Characteristics and Timing Host Port Timing HREQ (Output) HEN (Input) HA0-HA2 (Input) HR/W (Input) H0-H7 (Output) Figure 26 Host Read Cycle (Non-DMA Mode) HREQ (Output) HEN (Input) HA0-HA2 (Input) HR/W (Input) H0-H7 (Input) Figure 27 Host Write Cycle ...
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Freescale Semiconductor, Inc. HREQ (Output) 116 HACK (Input) 107 106 H0-H7 (Output) Figure 28 Host Read Cycle (DMA Mode) HREQ (Output) 116 HACK (Input) 104 H0-H7 (Input) Figure 29 Host Write Cycle (DMA Mode) MOTOROLA For More Information On This ...
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AC Electrical Characteristics and Timing SSI Timing Synchronous Serial Interfaces (SSI) Timing ( ± 10 FST (Transmit Frame Sync) FSR (Receive Frame Sync) = SCx1 Pin Internal Clock, Asynchronous ...
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Freescale Semiconductor, Inc. MOTOROLA For More Information On This Product, DSP56156 Data Sheet Go to: www.freescale.com AC Electrical Characteristics and Timing SSI Timing 45 ...
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AC Electrical Characteristics and Timing SSI Timing Table 20 Synchronous Serial Interfaces Timing (continued) Num 140 FSR Input (bl) High before SCK Falling Edge 141 FSR Input (wl) High before SCK Falling Edge 142 FSR Input Hold Time after SCK ...
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Freescale Semiconductor, Inc. 130 131 133 SCK (Input/Output) 134 FSR (Bit) Out FSR (Word) Out Data In 140 FSR (Bit) In FSR (Word) In Flags In Figure 30 SSI Receiver Timing MOTOROLA For More Information On This Product, 132 135 ...
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AC Electrical Characteristics and Timing Timer Timing 133 SCK (Input/Output) FST (Bit) Out FST (Word) Out Data Out 152 FST (Bit) In FST (Word) In Flags Out NOTE: In the Network mode, output flag transitions can occur at the start ...
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Freescale Semiconductor, Inc. Timer Timing ( ± 10 -40 to +125 Num Characteristic 170 TIN Valid to CLKO Low (Setup time) 171 CLKO Low to TIN Invalid (Hold time) 172 ...
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AC Electrical Characteristics and Timing OnCE Port Timing OnCE TM Port Timing ( ± 10 Num 180 DSCK High to DSO Valid 181 DSI Valid to DSCK Low (Setup) 182 DSCK Low to DSI ...
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Freescale Semiconductor, Inc. DSCK (Input) Figure 33 OnCE Port Serial Clock Timing DR (Input) DSO (Output) Figure 34 OnCE Port Acknowledge Timing DSCK (Input) 180 DSO (Output) DSI (Input) 181 NOTE: Three-state, external pull-down resistor Figure 35 OnCE Port Data ...
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Pin-out and Package Top View Pin-out and Package Information GND4 CC3 D4 D5 GND5 GND6 D10 D11 V CC4 D12 D13 GND7 D14 D15 CCA SPKP SPKM GNDA VDIV ...
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Freescale Semiconductor, Inc. MODA/IRQA RESET STD0/PC0 SRD0/PC1 SCK0/PC2 SC10/PC3 SC00/PC4 TIN/PC10 V CC7 TOUT/PC11 HA0/PB8 GND10 HA1/PB9 HA2/PB10 HR/W/PB11 HEN/PB12 HACK/PB14 HREQ/PB13 H0/PB0 H1/PB1 STD1/PC5 SRD1/PC6 H4/PB4 H3/PB3 H2/PB2 V CC6 H5/PB5 H6/PB6 57 NOTE: An OVERBAR indicates the signal ...
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Pin-out and Package General Purpose I/O Table 23 NOTES Tables 23, 24, and 25, OVERBAR indicates the signal is asserted when the voltage = ground (active low). 2. For more information on power and ground, see Table 26 ...
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Freescale Semiconductor, Inc. MOTOROLA For More Information On This Product, DSP56156 Data Sheet Go to: www.freescale.com Pin-out and Package Pin Number 55 ...
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Pin-out and Package Signal Name DSP56156 Pin Identification by Pin Number Table 24 112-pin Package Signal Name Package Pin # 1 GND4 CC3 GND5 ...
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Freescale Semiconductor, Inc. MOTOROLA For More Information On This Product, DSP56156 Data Sheet Go to: www.freescale.com Pin-out and Package Signal Name 57 ...
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Pin-out and Package DSP56156 Pin Identification by Signal Name Table 25 112-pin Package Signal Name Pin # 100 A9 102 A10 105 ...
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Freescale Semiconductor, Inc. MOTOROLA For More Information On This Product, DSP56156 Data Sheet Go to: www.freescale.com Pin-out and Package 59 ...
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Pin-out and Package DSP56156 Pin Identification by Signal Name (continued) Table 25 112-pin Package Signal Name Pin # 60 PB2 61 PB3 62 PB4 58 PB5 57 PB6 56 PB7 74 PB8 72 PB9 71 PB10 70 PB11 69 PB12 ...
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CQFP MOTOROLA Freescale Semiconductor, Inc. DSP56156 Data Sheet For More Information On This Product, Go to: www.freescale.com Pin-out and Package 61 ...
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Pin-out and Package S 0.20 (0.008 L 0.20 (0.008 L PIN 1 112 Identifier 108 Place A1 DATUM -H- PLANE ...
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Freescale Semiconductor, Inc. MOTOROLA For More Information On This Product, DSP56156 Data Sheet Go to: www.freescale.com Pin-out and Package 112 TQFP 63 ...
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Pin-out and Package 0.200 (0.008 PIN 1 112 Identifier 1 VIEW Y - 0.050 (0.002) C -H- C1 VIEW AB NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M, 1982. 2. Controlling ...
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Design Considerations Heat Dissipation Power, Ground, and Noise Design Considerations Heat Dissipation The average chip junction temperature can be obtained from Where ambient temperature ...
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Freescale Semiconductor, Inc. capacitor lead. The use of at least a four lay- er board is recommended, employing two inner layers as V and GND planes. All CC output pins on this DSP have fast rise and fall times. Printed ...
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Design Considerations Power Consumption Power Consumption ( ± 10 The DC electrical characteristics of this device are shown in Table 27. Power consumption is application dependant. The data in Table 27 is collected ...
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Freescale Semiconductor, Inc. Host Port Considerations Careful synchronization is required when reading multi-bit registers that are written by another asynchronous system. This is a com- mon problem when two asynchronous sys- tems are connected. The situation exists in the host ...
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Design Considerations DSP Programming Considerations Bus Operation DSP Programming Considerations 1. Synchronization of Status Bits from Host to DSP DMA, HF1, HF0, and HCP, HTDE, and HRDF status bits are set or cleared by the host processor side of the ...
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Freescale Semiconductor, Inc. Analog I/O Considerations Figure 44 describes the recommended analog I/O and power supply configurations. The two analog inputs are electrically identical. When one is not used, it can be left floating. When used coupling capacitor ...
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Design Considerations Analog I/O Considerations Figure 45 shows three possible single-ended output configurations. Configuration (a) is highly recommended. For configurations (b) and (c coupling capacitor is required since the load resistor is tied to GNDA. VREF V CCA ...
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Freescale Semiconductor, Inc. A four level board is recommended. The top layer (directly under the parts) and the bottom layer should be interconnect layers. The two center layers should be power and ground. Ground and power planes should be completely ...
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Design Considerations Analog I/O Considerations SPK OUT Figure 48 Suggested Bottom Layer Routing The output should be used differentially if at all possible. Analog signal traces should be shielded by running traces connected to analog ground ...
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Freescale Semiconductor, Inc. BIAS AUX MIC 28 Ideal Choice — Two separate power supplies. Ground planes connected with a single trace as close as possible to the V pin on the codec. CCA 10 BIAS AUX MIC 28 Voltage Regulator ...
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... Package Type Voltage Ceramic Quad Flat 5 V Pack (CQFP Plastic Thin Quad Flat Pack (TQFP) 70 Freescale Semiconductor, Inc. Frequency Pin Count (MHz) 112 112 DSP56156 Data Sheet For More Information On This Product, Go to: www.freescale.com Order Number 40 DSP56156FE40 60 DSP56156FE60 40 DSP56156FV40 60 DSP56156FV60 MOTOROLA ...
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Freescale Semiconductor, Inc. Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or ...