DSP56156FV40 MOTOROLA [Motorola, Inc], DSP56156FV40 Datasheet - Page 39

• Manufacturer Part Number: DSP56156FV40
• Description: 16-bit Digital Signal Processor
• Manufacturer: MOTOROLA [Motorola, Inc]

Host Port Timing
(V
Active low lines should be “pulled up” in a manner consistent with the AC and DC specifica-
tions.
MOTOROLA
CC
Num
100
101
102
103
104
105
106
107
108
109
= 5.0 V dc ± 10%, T
t
HSDL
tHSDL Host Synchronous Delay
(See Note 1)
HEN/HACK Assertion Width
(See Notes 2, 4)
HEN/HACK Deassertion Width
(See Note 2)
Minimum Cycle Time Between Two
HEN Assertion for Consecutive
CVR, ICR, ISR Reads
Host Data Input Setup Time before
HEN/HACK Deassertion
Host Data Input Hold Time after
HEN/HACK Deassertion
HEN/HACK Assertion to Output
Data Active from High Impedance
HEN/HACK Assertion to Output
Data Valid
HEN/HACK Deassertion to Output
Data High Impedance
Output Data Hold Time after
HEN/HACK Deassertion
t
cyc = Clock cycle =
suh
T = I
= Host Synchronization Delay Time
= Host Processor Data Setup Time
Characteristic
CYC
• CVR, ICR, ISR Read
• Read
• Write
Freescale Semiconductor, Inc.
/ 4
For More Information On This Product,
J
= -40 to +125 C, C
Go to: www.freescale.com
1
/
2
instruction cycle= 2 T cycle
Table 19 Host Port Timing
DSP56156 Data Sheet
32+t
2T+36
4T+36
Min
32
31
—
—
L
T
5
7
0
5
suh
40 MHz
= 50 pF + 1 TTL Load)
Max
3T
—
—
—
—
—
—
—
32
20
—
(See Note 1)
29+t
2T+33
4T+33
Min
29
29
—
—
T
4
6
0
5
suh
50 MHz
AC Electrical Characteristics and Timing
Max
18.5
3T
29
—
—
—
—
—
—
—
—
26+t
2T+30
4T+30
Min
26
27
—
—
T
3
5
0
4
suh
60 MHz
Host Port Timing
Max
3T
—
—
—
—
—
—
—
26
17
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
39