DSP56156FV40 MOTOROLA [Motorola, Inc], DSP56156FV40 Datasheet - Page 40

• Manufacturer Part Number: DSP56156FV40
• Description: 16-bit Digital Signal Processor
• Manufacturer: MOTOROLA [Motorola, Inc]

40
AC Electrical Characteristics and Timing
Host Port Timing
Num
110
111
112
113
114
115
116
117
118
119
120
HR/W Low Setup Time before HEN Assertion
HR/W Low Hold Time after HEN Deassertion
HR/W High Setup Time to HEN Assertion
HR/W High Hold Time after HEN/HACK
Deassertion
HA0-HA2 Setup Time before HEN Assertion
HA0-HA2 Hold Time after HEN Deassertion
DMA HACK Assertion to HREQ Deassertion
(See Note 3)
DMA HACK Deassertion to HREQ
Assertion (See Note 3)
Delay from HEN Deassertion to HREQ
Assertion for RXL Read (See Note 3)
Delay from HEN Deassertion to HREQ
Assertion for TXL Write (See Note 3)
Delay from HEN Assertion to HREQ
Deassertion for RXL Read, TXL Write
(See Note 3)
NOTES:
1. “Host Synchronization Delay (tHSDL)” is the time period required for the DSP56156 to sample any
2. See Host Port Considerations.
3. HREQ is pulled up by 1 k
4. Only if two consecutive reads from one of these registers are executed.
Characteristic
external asynchronous input signal, determine whether it is high or low, and synchronize it to the
internal clock.
for DMA RXL Read
Table 19 Host Port Timing (continued)
for All Other Cases
for DMA TXL Write
Freescale Semiconductor, Inc.
For More Information On This Product,
DSP56156 Data Sheet
Go to: www.freescale.com
+3T+5
+2T+5
+3T+5
+2T+5
t
t
t
t
Min
HSDL
HSDL
HSDL
HSDL
6
6
5
9
8
5
5
5
6
40 MHz
Max
+37
+37
2T
2T
—
—
—
—
—
—
—
—
—
—
—
+2T+5
+3T+5
+2T+5
t
t
t
t
3T+5
Min
HSDL
HSDL
HSDL
HSDL
7.5
5
5
5
4
7
5
5
5
50 MHz
Max
+36
+36
2T
2T
—
—
—
—
—
—
—
—
—
—
—
+3T+4
+2T+4
+3T+4
+2T+4
t
t
t
t
Min
HSDL
HSDL
HSDL
HSDL
4
4
4
3
6
6
4
4
5
60 MHz
Max
+35
+35
2T
2T
—
—
—
—
—
—
—
—
—
—
—
MOTOROLA
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns