ADSP-21266SKBC-2B AD [Analog Devices], ADSP-21266SKBC-2B Datasheet - Page 20

• Manufacturer Part Number: ADSP-21266SKBC-2B
• Description: SHARC Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-21266
Reset
See
Table 12. Reset
1
Interrupts
The timing specification in
FLAG0, FLAG1, and FLAG2 pins when they are configured as
IRQ0, IRQ1, and IRQ2 interrupts. Also applies to DAI_P20
pins when configured as interrupts.
Table 13. Interrupts
Core Timer
The timing specification in
FLAG3 when it is configured as the core timer (CTIMER).
Table 14. Core Timer
Parameter
Timing Requirements
t
t
Parameter
Timing Requirement
t
Parameter
Switching Characteristic
t
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 µs while RESET is low, assuming
WRST
SRST
IPW
WCTIM
stable VDD and CLKIN (not including start-up time of external clock oscillator).
(C TIM E R )
Table 12
F L G 3
and
Figure
RESET Pulse Width Low
RESET Setup Before CLKIN Low
IRQx Pulse Width
CTIMER Pulse Width
9.
RESET
CLKIN
Table 13
Table 14
and
and
DAI_P20–1
1
Figure 10
Figure 11
(FLG2–0)
(IRQ2–0)
applies to the
applies to
Rev. B | Page 20 of 44 | May 2005
Figure 11. Core Timer
Figure 10. Interrupts
–
Figure 9. Reset
t
1
WRST
Min
4t
8
t
IPW
CK
Min
4 × t
CCLK
t
W C T IM
– 1
Min
2 × t
CCLK
t
SRST
+2
Max
Max
Max
Unit
ns
ns
Unit
ns
Unit
ns