ADSP-21266SKBC-2B AD [Analog Devices], ADSP-21266SKBC-2B Datasheet - Page 29

• Manufacturer Part Number: ADSP-21266SKBC-2B
• Description: SHARC Embedded Processor
• Manufacturer: AD [Analog Devices]

Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the specifications in
Table
1) frame sync delay and frame sync setup and hold; 2) data delay
and data setup and hold; and 3) SCLK width.
Table 24. Serial Ports—External Clock
1
2
Table 25. Serial Ports—Internal Clock
1
2
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
Referenced to sample edge.
Referenced to drive edge.
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
Referenced to the sample edge.
Referenced to drive edge.
SFSE
HFSE
SDRE
HDRE
SCLKW
SCLK
DFSE
HOFSE
DDTE
HDTE
SFSI
HFSI
SDRI
HDRI
DFSI
HOFSI
DFSI
HOFSI
DDTI
HDTI
SCLKIW
26,
Table
27,
FS Setup Before SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
FS Hold After SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
Receive Data Setup Before Receive SCLK
Receive Data Hold After SCLK
SCLK Width
SCLK Period
FS Delay After SCLK
(Internally Generated FS in Either Transmit or Receive Mode)
FS Hold After SCLK
(Internally Generated FS in Either Transmit or Receive Mode)
Transmit Data Delay After Transmit SCLK
Transmit Data Hold After Transmit SCLK
FS Setup Before SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
FS Hold After SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
Receive Data Setup Before SCLK
Receive Data Hold After SCLK
FS Delay After SCLK (Internally Generated FS in Transmit Mode)
FS Hold After SCLK (Internally Generated FS in Transmit Mode)
FS Delay After SCLK (Internally Generated FS in Receive Mode)
FS Hold After SCLK (Internally Generated FS in Receive Mode)
Transmit Data Delay After SCLK
Transmit Data Hold After SCLK
Transmit or Receive SCLK Width
Figure
21, and
Figure 22
must be confirmed:
Table
1
1
2
2
1
24,
Rev. B | Page 29 of 44 | May 2005
Table
2
1
2
25,
Serial port signals (SCLK, FS, DxA,/DxB) are routed to the
DAI_P20
cations provided below are valid at the DAI_P20
2
2
1
1
1
1
2
2
2
2
–
1 pins using the SRU. Therefore, the timing specifi-
Min
2.5
2.5
2.5
2.5
7
20
2
2
Min
6
1.5
6
1.5
–1.0
–1.0
–1.0
0.5t
SCLK
– 2
Max
3
3
3
0.5t
Max
7
7
SCLK
+ 2
ADSP-21266
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1 pins.