ADSP-21266SKBC-2B AD [Analog Devices], ADSP-21266SKBC-2B Datasheet - Page 26

• Manufacturer Part Number: ADSP-21266SKBC-2B
• Description: SHARC Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-21266
Table 21. 16-Bit Memory Read Cycle
1
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
D = (data cycle duration) × t
H = t
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
DRS
DRH
ALEW
ALERW
ADAS
ADAH
ALEHZ
RW
CCLK
(if a hold cycle is specified, else H = 0)
Address/Data 15–0 Setup Before RD high
Address/Data 15–0 Hold After RD high
ALE Pulse Width
ALE Deasserted to Read/Write Asserted
Address/Data 15–0 Setup Before ALE Deasserted
Address/Data 15–0 Hold After ALE Deaserted
ALE Deasserted
RD Pulse Width
AD15-0
ALE
WR
RD
CCLK
1
to Address/Data 15–0 In High Z
VALID ADDRESS
t
ADAS
t
ALEW
Figure 18. 16-Bit Memory Read Cycle
Rev. B | Page 26 of 44 | May 2005
t
ADAH
t
t
ALERW
ALEHZ
1
1
t
RW
t
VALID DATA
DRS
Min
3.3
0
2 × t
1 × t
2.5 × t
0.5 × t
0.5 × t
D – 2
CCLK
CCLK
CCLK
CCLK
CCLK
t
DRH
– 2
– 0.5
– 2.0
– 0.8
– 0.8
Max
0.5t
CCLK
+ 2.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns