ADSP-21266SKBC-2B AD [Analog Devices], ADSP-21266SKBC-2B Datasheet - Page 34

• Manufacturer Part Number: ADSP-21266SKBC-2B
• Description: SHARC Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-21266
SPI Interface Protocol—Master
Table 30. SPI Interface Protocol—Master
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
SSPIDM
HSPIDM
SPICLKM
SPICHM
SPICLM
DDSPIDM
HDSPIDM
SDSCIM
HDSM
SPITDM
CPHASE = 1
CPHASE = 0
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
SPICLK
(CP = 0)
SPICLK
(CP = 1)
(INPUT)
(INPUT)
FLG3-0
MISO
MOSI
MOSI
MISO
t
S S P I D M
Data Input Valid to SPICLK Edge (Data Input Setup Time)
SPICLK Last Sampling Edge to Data Input Not Valid
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
FLAG3
Last SPICLK Edge to FLAG3
Sequential Transfer Delay
t
S D S C I M
–
VALID
0 OUT (SPI Device Select) Low to First SPICLK Edge
MSB
t
t
MSB
S P I C H M
S P IC LM
VALID
MSB
t
H S P ID M
t
t
D D S P I D M
t
t
S S P ID M
MSB
S P IC LM
S P I C H M
Figure 25. SPI Interface Protocol—Master
t
–
D D S P I D M
0 OUT High
Rev. B | Page 34 of 44 | May 2005
t
H S P I D M
t
H D S P I D M
t
t
S S P I D M
HDSPIDM
t
VALID
S P IC LK M
LSB
LSB
VALID
LSB
Min
5
2
8 × t
4 × t
4 × t
10
4 × t
4 × t
4 × t
t
H D S M
LSB
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
t
– 2
– 2
– 2
– 1
– 1
H S P I D M
t
S P I T D M
Max
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns