ADSP-BF522 AD [Analog Devices], ADSP-BF522 Datasheet - Page 16

• Manufacturer Part Number: ADSP-BF522
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-BF522/523/524/525/526/527
consumption, the internal voltage regulator can be programmed
to remove power to the processor core while keeping I/O power
supplied. While in the hibernate state, all external supplies
(V
ing the need for external buffers. V
times for correct hibernate operation. The voltage regulator can
be activated from this power down state either through an RTC
wakeup, a USB wakeup, an ethernet wakeup, or by asserting the
RESET pin, each of which then initiates a boot sequence. The
regulator can also be disabled and bypassed at the user’s
discretion.
The voltage regulator has two modes set by the VR
normal pulse width control of an external FET and the external
supply mode which can signal a power down during hibernate
to an external regulator. Set VR
regulator or set VR
the external mode VR
regulator is used, EXT_WAKE0 can control other power
sources in the system during the hibernate state. Both signals
are high-true for power-up and may be connected directly to the
low-true shut down input of many common regulators. The
mode of the SS/PG (Soft Start/Power Good) signal also changes
according to the state of VR
tor, the SS/PG pin is Soft Start, and when using an external
regulator, it is Power Good. The Soft Start feature is recom-
mended to reduce the inrush currents and to reduce V
voltage overshoot when coming out of hibernate or changing
voltage levels. The Power Good (PG) input signal allows the
processor to start only after the internal voltage has reached a
chosen level. In this way, the startup time of the external regula-
tor is detected after hibernation. For a complete description of
Soft Start and Power Good functionality, refer to the ADSP-
BF52x Blackfin Processor Hardware Reference.
NOTE: DESIGNER SHOULD MINIMIZE
TRACE LENGTH TO FDS9431A.
2.25V TO 3.6V
INPUT VOLTAGE
RANGE
DDEXT
100μF
+
LOW ESR
10μ F
, V
Figure 5. ADSP-BF523/525/527 Voltage Regulator Circuit
INDUCTANCE WIRE
SHORT AND LOW-
DDMEM
100nF
FDS9431A
, V
(LOW-INDUCTANCE)
SEL
DDUSB
V
OUT
to GND to use the internal regulator. In
DDEXT
, V
becomes EXT_WAKE1. If the internal
SEE H/W REFERENCE,
SYSTEM DESIGN CHAPTER,
TO DETERMINE VALUE
DDOTP
SEL
ZHCS1000
. When using an internal regula-
SEL
) can still be applied, eliminat-
10μH
SET OF DECOUPLING
to V
DDRTC
CAPACITORS
100μF
DDEXT
100μF
must be applied at all
+
+
to use an external
Rev. PrG | Page 16 of 80 | February 2009
SEL
pin—the
DDINT
VR
EXT_WAKE1
VR
GND
SS/PG
V
V
DDEXT
DDINT
OUT
SEL
ADSP-BF522/524/526 VOLTAGE REGULATION
The ADSP-BF522/524/526 processor requires an external volt-
age regulator to power the V
power consumption, the external voltage regulator can be sig-
naled through EXT_WAKE0 or EXT_WAKE1 to remove power
from the processor core. These identical signals are high-true
for power-up and may be connected directly to the low-true
shut down input of many common regulators. While in the
hibernate state, all external supplies (V
V
buffers. V
operation. The external voltage regulator can be activated from
this power down state either through an RTC wakeup, a USB
wakeup, an ethernet wakeup, or by asserting the RESET pin,
each of which then initiates a boot sequence. EXT_WAKE0 or
EXT_WAKE1 indicate a wakeup to the external voltage regula-
tor. The Power Good (PG) input signal allows the processor to
start only after the internal voltage has reached a chosen level. In
this way, the startup time of the external regulator is detected
after hibernation. For a complete description of the Power Good
functionality, refer to the ADSP-BF52x Blackfin Processor Hard-
ware Reference.
CLOCK SIGNALS
The processor can be clocked by an external crystal, a sine wave
input, or a buffered, shaped clock derived from an external
clock oscillator.
If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
Alternatively, because the processor includes an on-chip oscilla-
tor circuit, an external crystal may be used. For fundamental
frequency operation, use the circuit shown in
lel-resonant, fundamental frequency, microprocessor-grade
crystal is connected across the CLKIN and XTAL pins. The on-
chip resistance between CLKIN and the XTAL pin is in the 500
k range. Further parallel resistors are typically not recom-
mended. The two capacitors and the series resistor shown in
Figure 6
The capacitor and resistor values shown in
values only. The capacitor values are dependent upon the crystal
manufacturers’ load capacitance recommendations and the PCB
physical layout. The resistor value depends on the drive level
DDOTP
) can still be applied, eliminating the need for external
fine tune phase and amplitude of the sine frequency.
DDRTC
must be applied at all times for correct hibernate
Preliminary Technical Data
DDINT
domain. To reduce standby
DDEXT
Figure 6
, V
Figure
DDMEM
are typical
, V
6. A paral-
DDUSB
,