ADSP-BF522 AD [Analog Devices], ADSP-BF522 Datasheet - Page 52

• Manufacturer Part Number: ADSP-BF522
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-BF522/523/524/525/526/527
Serial Peripheral Interface (SPI) Port—Master Timing
Table 41
Table 41. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Timing Requirements
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
SSPIDM
SDSCIM
SPICHM
SPICLM
SPICLK
HDSM
SPITDM
DDSPIDM
HDSPIDM
HSPIDM
and
Data Input Valid to SCK Edge (Data
Input Setup)
SCK Sampling Edge to Data Input
Invalid
SPISELx low to First SCK Edge
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
Last SCK Edge to SPISELx High
Sequential Transfer Delay
SCK Edge to Data Out Valid (Data
Out Delay)
SCK Edge to Data Out Invalid (Data
Out Hold)
CPHA = 1
CPHA = 0
Figure 26
(OUTPUT)
(INPUT)
(OUTPUT)
(INPUT)
(OUTPUT)
(CPOL = 0)
(CPOL = 1)
SPISELx
(OUTPUT)
(OUTPUT)
MISO
MISO
MOSI
MOSI
SCK
SCK
describe SPI port master operations.
t
SSPIDM
t
SDSCIM
MSB VALID
MSB
t
t
SPICHM
SPICLM
Figure 26. Serial Peripheral Interface (SPI) Port—Master Timing
MSB VALID
t
2 t
2 t
2 t
2 t
2 t
4 t
HSPIDM
V
Rev. PrG | Page 52 of 80 | February 2009
t
Min
11.6
–1.5
–1.0
t
t
DDEXT
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
HDSPIDM
MSB
SPICLM
SPICHM
–1.5
–1.5
–1.5
–1.5
–1.5
–1.5
ADSP-BF522/524/526
t
= 1.8 V
HDSPIDM
Max
6
2 t
2 t
2 t
4 t
2 t
2 t
V
DDEXT
11.6
–1.5
–1.0
Min
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
t
= 2.5/3.3 V
DDSPIDM
–1.5
–1.5
–1.5
–1.5
–1.5
–1.5
LSB VALID
t
t
t
SSPIDM
SPICLK
DDSPIDM
Max
6
LSB VALID
LSB
2 t
2 t
2 t
2 t
2 t
4 t
V
Min
11.6
–1.5
–1.0
DDEXT
SCLK
SCLK
SCLK
SCLK
SCLK
t
Preliminary Technical Data
SCLK
HDSM
LSB
t
HSPIDM
–1.5
–1.5
–1.5
–1.5
–1.5
–1.5
ADSP-BF523/525/527
= 1.8 V
Max
t
SPITDM
6
2 t
2 t
2 t
2 t
2 t
4 t
V
DDEXT
Min
–1.5
–1.0
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
9.6
= 2.5/3.3 V
–1.5
–1.5
–1.5
–1.5
–1.5
–1.5
Max Unit
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns