ADSP-BF522 AD [Analog Devices], ADSP-BF522 Datasheet - Page 41

• Manufacturer Part Number: ADSP-BF522
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
NAND Flash Controller Interface Timing
Table 33
Page 43
Table 33. NAND Flash Controller Interface Timing
1
2
Parameter
Write Cycle
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
Read Cycle
Switching Characteristics
t
t
t
t
t
Timing Requirements
t
t
Write Followed by Read
Switching Characteristics
t
WR_DLY and RD_DLY are defined in the NFC_CTL register.
The only parameter that differs from 1.8V to 2.5/3.3V operation is t
CWL
CH
CLEWL
CLH
ALEWL
ALH
WP
WHWL
WC
DWS
DWH
CRL
CRH
RP
RHRL
RC
DRS
DRH
WHRL
1
1
1
1
1
describe NAND Flash Controller Interface operations.
and
Figure 12 on Page 41
ND_CE Setup Time to AWE Low
ND_CE Hold Time From AWE High
ND_CLE Setup Time to AWE Low
ND_CLE Hold Time From AWE high
ND_ALE Setup Time to AWE Low
ND_ALE Hold Time From AWE High
AWE Low to AWE high
AWE High to AWE Low
AWE Low to AWE Low
Data Setup Time for a Write Access
Data Hold Time for a Write Access
ND_CE Setup Time to ARE Low
ND_CE Hold Time From ARE High
ARE Low to ARE High
ARE High to ARE Low
ARE Low to ARE Low
Data Setup Time for a Read Transaction
Data Hold Time for a Read Transaction
AWE High to ARE Low
ND_D 0 -D 7
ND_CLE
ND_ALE
through
ND_CE
AWE
Figure 12. NAND Flash Controller Interface Timing - Command Write Cycle
Figure 16 on
t ALEWL
t CLEWL
Rev. PrG | Page 41 of 80 | February 2009
t CWL
DRS
, which is 8.0ns at 2.5/3.3V and is 11ns at 1.8V.
t DWS
t WP
t DWH
t CLH
t CH
(WR_DLY +1.0) t
(WR_DLY +5.0) t
(WR_DLY +1.5) t
(RD_DLY +1.0) t
(RD_DLY +5.0) t
t ALH
ADSP-BF522/523/524/525/526/527
5.0
1.0 t
3.0 t
2.5 t
2.5 t
4.0 t
2.5 t
1.0 t
3.0 t
4.0 t
Min
8.0
0.0
0.0
0.0
t
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
2
– 4
– 4
– 4
– 4
– 4
– 4
– 4
– 4
– 4
– 4
SCLK
SCLK
SCLK
SCLK
SCLK
– 4
– 4
– 4
– 4
– 4
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns