ADSP-BF606 AD [Analog Devices], ADSP-BF606 Datasheet - Page 14

• Manufacturer Part Number: ADSP-BF606
• Description: Blackfin Dual Core
• Manufacturer: AD [Analog Devices]

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
The CAN controller offers the following features:
An additional crystal is not required to supply the CAN clock, as
the CAN clock is derived from a system clock through a pro-
grammable divider.
10/100 Ethernet MAC
The processor can directly connect to a network by way of an
embedded fast Ethernet media access controller (MAC) that
supports both 10-BaseT (10M bits/sec) and 100-BaseT (100M
bits/sec) operation. The 10/100 Ethernet MAC peripheral on the
processor is fully compliant to the IEEE 802.3-2002 standard
and it provides programmable features designed to minimize
supervision, bus use, or message processing by the rest of the
processor system.
Some standard features are:
Some advanced features are:
• 32 mailboxes (8 receive only, 8 transmit only, 16 configu-
• Dedicated acceptance masks for each mailbox.
• Additional data filtering on first two bytes.
• Support for both the standard (11-bit) and extended (29-
• Support for remote frames.
• Active or passive network support.
• CAN wakeup from hibernation mode (lowest static power
• Interrupts, including: TX complete, RX complete, error
• Support and RMII protocols for external PHYs
• Full duplex and half duplex modes
• Media access management (in half-duplex operation)
• Flow control
• Station management: generation of MDC/MDIO frames
• Automatic checksum computation of IP header and IP
• Independent 32-bit descriptor-driven receive and transmit
• Frame status delivery to memory through DMA, including
• Tx DMA support for separate descriptors for MAC header
• Convenient frame alignment modes
• 47 MAC management statistics counters with selectable
• Advanced power management
• Magic packet detection and wakeup frame filtering
rable for receive or transmit).
bit) identifier (ID) message formats.
consumption mode).
and global.
for read-write access to PHY registers
payload fields of Rx frames
DMA channels
frame completion semaphores for efficient buffer queue
management in software
and payload to eliminate buffer copy operations
clear-on-read behavior and programmable interrupts on
half maximum value
Rev. PrD | Page 14 of 44 | March 2012
IEEE 1588 Support
The IEEE 1588 standard is a precision clock synchronization
protocol for networked measurement and control systems. The
processor includes hardware support for IEEE 1588 with an
integrated precision time protocol synchronization engine
(PTP_TSYNC). This engine provides hardware assisted time
stamping to improve the accuracy of clock synchronization
between PTP nodes. The main features of the engine are:
USB 2.0 On-the-Go Dual-Role Device Controller
The USB 2.0 OTG dual-role device controller provides a low-
cost connectivity solution for the growing adoption of this bus
standard in industrial applications, as well as consumer mobile
devices such as cell phones, digital still cameras, and MP3 play-
ers. The USB 2.0 controller allows these devices to transfer data
using a point-to-point USB connection without the need for a
PC host. The module can operate in a traditional USB periph-
eral-only mode as well as the host mode presented in the On-
the-Go (OTG) supplement to the USB 2.0 specification.
The USB clock (USB_CLKIN) is provided through a dedicated
external crystal or crystal oscillator.
The USB On-the-Go dual-role device controller includes a
Phase Locked Loop with programmable multipliers to generate
the necessary internal clocking frequency for USB.
POWER AND CLOCK MANAGEMENT
The processor provides four operating modes, each with a dif-
ferent performance/power profile. When configured for a 0 volt
internal supply voltage (V
nate state. Control of clocking to each of the processor
peripherals also reduces power consumption. See
summary of the power settings for each mode.
Crystal Oscillator (SYS_XTAL)
The processor can be clocked by an external crystal,
sine wave input, or a buffered, shaped clock derived from an
external clock oscillator. If an external clock is used, it should be
a TTL compatible signal and must not be halted, changed, or
operated below the specified frequency during normal opera-
tion. This signal is connected to the processor’s SYS_CLKIN
• Support for 802.3Q tagged VLAN frames
• Programmable MDC clock rate and preamble suppression
• Support for both IEEE 1588-2002 and IEEE 1588-2008 pro-
• Hardware assisted time stamping capable of up to 12.5 ns
• Lock adjustment
• Automatic detection of IPv4 and IPv6 packets, as well as
• Multiple input clock sources (SCLK0, RMII clock, external
• Programmable pulse per second (PPS) output
• Auxiliary snapshot to time stamp external events
tocol standards
resolution
PTP messages
clock)
Preliminary Technical Data
DD_INT
), the processor enters the hiber-
Table 5
(Figure
for a
6) a