ADSP-BF606 AD [Analog Devices], ADSP-BF606 Datasheet - Page 21

• Manufacturer Part Number: ADSP-BF606
• Description: Blackfin Dual Core
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
Table 7. Processor Multiplexing Scheme (Continued)
Signal Name
PA_14/SMC0_A19/EPPI2_D14/LP1_D6
PA_15/SMC0_A20/EPPI2_D15/LP1_D7
Port B
PB_00/SMC0_NORCLK/EPPI2_CLK/LP0_CLK
PB_01/SMC0_AMS1/EPPI2_FS1/LP0_ACK
PB_02/SMC0_A13/EPPI2_FS2/LP1_ACK
PB_03/SMC0_A16/EPPI2_FS3/LP1_CLK
PB_04/SMC0_AMS2/SMC0_ABE0/SPT0_AFS
PB_05/SMC0_AMS3/SMC0_ABE1/SPT0_ACLK
PB_06/SMC0_A21/SPT0_ATDV/TM0_ACLK4
PB_07/SMC0_A22/EPPI2_D16/SPT0_BFS
PB_08/SMC0_A23/EPPI2_D17/SPT0_BCLK
PB_09/SMC0_BGH/SPT0_AD0/TM0_ACLK2
PB_10/SMC0_A24/SPT0_BD1/TM0_ACLK0
PB_11/SMC0_A25/SPT0_BD0/TM0_ACLK3
PB_12/SMC0_BG/SPT0_BTDV/SPT0_AD1/
TM0_ACLK1
PB_13/ETH0_TXEN/EPPI1_FS1/TM0_ACI6
PB_14/ETH0_REFCLK/EPPI1_CLK
PB_15/ETH0_PTPPPS/EPPI1_FS3
Port C
PC_00/ETH0_RXD0/EPPI1_D00
PC_01/ETH0_RXD1/EPPI1_D01
PC_02/ETH0_TXD0/EPPI1_D02
PC_03/ETH0_TXD1/EPPI1_D03
PC_04/ETH0_RXERR/EPPI1_D04
PC_05/ETH0_CRS/EPPI1_D05
PC_06/ETH0_MDC/EPPI1_D06
PC_07/ETH0_MDIO/EPPI1_D07
PC_08/EPPI1_D08
PC_09/ETH1_PTPPPS/EPPI1_D09
PC_10/EPPI1_D10
PC_11/EPPI1_D11/ETH_PTPAUXIN
PC_12/SPI0_SEL7/EPPI1_D12
PC_13/SPI0_SEL6/EPPI1_D13/ETH_PTPCLKIN
PC_14/SPI1_SEL7/EPPI1_D14
PC_15/SPI0_SEL4/EPPI1_D15
Port D
PD_00/SPI0_D2/EPPI1_D16/SPI0_SEL3
PD_01/SPI0_D3/EPPI1_D17/SPI0_SEL2
PD_02/SPI0_MISO
PD_03/SPI0_MOSI
PD_04/SPI0_CLK
PD_05/SPI1_CLK/TM0_ACLK7
PD_06/ETH0_PHYINT/EPPI1_FS2/TM0_ACI5
PD_07/UART0_TX/TM0_ACI3
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Function
PA Position 14/SMC0 Address 19/EPPI2 Data 14/LP1 Data 6
PA Position 15/SMC0 Address 20/EPPI2 Data 15/LP1 Data 7
PB Position 0/SMC0 NOR Clock/EPPI2 Clock/LP0 Clock
PB Position 1/SMC0 Memory Select 1/EPPI2 Frame Sync 1 (HSYNC)/LP0 Acknowledge
PB Position 2/SMC0 Address 13/EPPI2 Frame Sync 2 (VSYNC)/LP1 Acknowledge
PB Position 3/SMC0 Address 16/EPPI2 Frame Sync 3 (FIELD)/LP1 Clock
PB Position 4/SMC0 Memory Select 2/SMC0 Byte Enable 0/SPORT0 Channel A Frame Sync
PB Position 5/SMC0 Memory Select 3/SMC0 Byte Enable 1/SPORT0 Channel A Clock
PB Position 6/SMC0 Address 21/SPORT0 Channel A Transmit Data Valid/
TIMER0 Alternate Clock 4
PB Position 7/SMC0 Address 22/EPPI2 Data 16/SPORT0 Channel B Frame Sync
PB Position 8/SMC0 Address 23/EPPI2 Data 17/SPORT0 Channel B Clock
PB Position 9/SMC0 Bus Grant Hang/SPORT0 Channel A Data 0/TIMER0 Alternate Clock 2
PB Position 10/SMC0 Address 24/SPORT0 Channel B Data 1/TIMER0 Alternate Clock 0
PB Position 11/SMC0 Address 25/SPORT0 Channel B Data 0/TIMER0 Alternate Clock 3
PB Position 12/SMC0 Bus Grant/SPORT0 Channel B Transmit Data Valid/ SPORT0 Channel A
Data 1/TIMER0 Alternate Clock 1
PB Position 13/ETH0 Transmit Enable/EPPI1 Frame Sync 1 (HSYNC)/
TIMER0 Alternate Capture Input 6
PB Position 14/ETH0 Reference Clock/EPPI1 Clock
PB Position 15/ETH0 PTP Pulse-Per-Second Output/EPPI1 Frame Sync 3 (FIELD)
PC Position 0/ETH0 Receive Data 0/EPPI1 Data 0
PC Position 1/ETH0 Receive Data 1/EPPI1 Data 1
PC Position 2/ETH0 Transmit Data 0/EPPI1 Data 2
PC Position 3/ETH0 Transmit Data 1/EPPI1 Data 3
PC Position 4/ETH0 Receive Error/EPPI1 Data 4
PC Position 5/ETH0 Carrier Sense/RMII Receive Data Valid/EPPI1 Data 5
PC Position 6/ETH0 Management Channel Clock/EPPI1 Data 6
PC Position 7/ETH0 Management Channel Serial Data/EPPI1 Data 7
PC Position 8/EPPI1 Data 8
PC Position 9/ETH1 PTP Pulse-Per-Second Output/EPPI1 Data 9
PC Position 10/EPPI1 Data 10
PC Position 11/EPPI1 Data 11/ETH PTP Auxiliary Trigger Input
PC Position 12/SPI0 Slave Select Output 7/EPPI1 Data 12
PC Position 13/SPI0 Slave Select Output 6/EPPI1 Data 13/ETH PTP Clock Input
PC Position 14/SPI1 Slave Select Output 7/EPPI1 Data 14
PC Position 15/SPI0 Slave Select Output 4/EPPI1 Data 15
PD Position 0/SPI0 Data 2/EPPI1 Data 16/SPI0 Slave Select Output 3
PD Position 1/SPI0 Data 3/EPPI1 Data 17/SPI0 Slave Select Output 2
PD Position 2/SPI0 Master In, Slave Out
PD Position 3/SPI0 Master Out, Slave In
PD Position 4/SPI0 Clock
PD Position 5/SPI1 Clock/TIMER0 Alternate Clock 7
PD Position 6/ETH0 RMII Management Data Interrupt/EPPI1 Frame Sync 2 (VSYNC)/
TIMER0 Alternate Capture Input 5
PD Position 7/UART0 Transmit/TIMER0 Alternate Capture Input 3
Rev. PrD | Page 21 of 44 | March 2012