ADSP-BF606 AD [Analog Devices], ADSP-BF606 Datasheet - Page 32

• Manufacturer Part Number: ADSP-BF606
• Description: Blackfin Dual Core
• Manufacturer: AD [Analog Devices]

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Clock Related Operating Conditions
Table 9
presented in the tables applies to all speed grades (found in
Automotive Products on Page
Figure 8
clocks and their available divider values.
Table 9. Clock Operating Conditions
1
2
Table 10. Phase-Locked Loop Operating Conditions
Parameter
f
f
f
f
f
f
Parameter
f
t
Rounded number. Actual test specification is a period of [TBD] ns.
CCLK
SYSCLK
SCLK0
SCLK1
DCLK
OCLK
SCLK0/1
PLLCLK
1, 2
1, 2
is equal to 1/f
describes the core clock timing requirements. The data
provides a graphical representation of the various
SCLK0/1
PLL Clock Frequency
.
CLKIN
Core Clock Frequency (CCLK ≥ SYSCLK, CSEL ≤ SYSSEL)
SYSCLK Frequency (SYSSEL ≤ DSEL)
SCLK0 Frequency
SCLK1 Frequency
DDR2/LPDDR Clock Frequency
Output Clock Frequency
43) except where expressly noted.
PLL
PLLCLK
Figure 8. Clock Relationships and Divider Values
Rev. PrD | Page 32 of 44 | March 2012
SYSSEL
(1-128)
(1-32)
CSEL
(1-32)
(1-32)
OSEL
DSEL
SYSCLK
CCLK
DCLK
OCLK
S1SEL
S0SEL
(1-4)
(1-4)
Preliminary Technical Data
Minimum
SCLK0
(PVP, ALL OTHER
PERIPHERALS)
SCLK1
(SPORTS, SPI, ACM)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Speed Grade
Maximum
Maximum
Unit
MHz
Unit
MHz
MHz
MHz
MHz
MHz
MHz