SAA7103 PHILIPS [NXP Semiconductors], SAA7103 Datasheet - Page 12

• Manufacturer Part Number: SAA7103
• Description: Digital video encoder
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Table 4 Cursor bit map
Table 5 Cursor modes
7.5
RGB input signals to be encoded to PAL or NTSC are
converted to the Y-C
colour difference signals are fed through low-pass filters
and formatted to a ITU-R BT.601 like 4 : 2 : 2 data stream
for further processing.
The matrix and formatting blocks can be bypassed for
Y-C
When the auxiliary VGA mode is selected, the output of the
cursor insertion block is immediately directed to the triple
DAC.
2001 Sep 25
0
1
2
...
6
7
...
254
255
00
01
10
11
PATTERN
CURSOR
BYTE
Digital video encoder
B
-C
RGB Y-C
R
graphics input.
row 0
column 3
row 0
column 7
row 0
column
11
row 0
column
27
row 0
column
31
row 31
column
27
row 31
column
31
D7
second cursor colour second cursor colour
first cursor colour
transparent
inverted input
...
...
B
CMODE = 0
D6
-C
R
B
-C
matrix
row 0
column 2
row 0
column 6
row 0
column
10
row 0
column
26
row 0
column
30
row 31
column
26
row 31
column
30
D5
R
colour space in this block. The
CURSOR MODE
...
...
D4
row 0
column 1
row 0
column 5
row 0
column 9
row 0
column
25
row 0
column
29
row 31
column
25
row 31
column
29
D3
first cursor colour
transparent
auxiliary cursor
colour
...
...
CMODE = 1
D2
row 0
column 0
row 0
column 4
row 0
column 8
row 0
column
24
row 0
column
28
row 31
column
24
row 31
column
28
D1
...
...
D0
12
7.6
The high quality horizontal scaler operates on the 4 : 2 : 2
data stream. Its control engines compensate the colour
phase offset automatically.
The scaler starts processing after a programmable
horizontal offset and continues with a number of input
pixels. Each input pixel is a programmable fraction of the
current output pixel (XINC/4096). A special case is
XINC = 0, this sets the scaling factor to 1.
If the SAA7102; SAA7103 input data is in accordance with
“ITU-R BT.656” , the scaler enters another mode. In this
event, XINC needs to be set to 2048 for a scaling factor
of 1. With higher values, upscaling will occur.
The phase resolution of the circuit is 12 bits, giving a
maximum offset of 0.2 after 800 input pixels. Small FIFOs
rearrange a 4 : 2 : 2 data stream at the scaler output.
7.7
The functions scaling, Anti-Flicker Filter (AFF) and
re-interlacing are implemented in the vertical scaler.
Besides the entire input frame, it receives the first and last
lines of the border to allow anti-flicker filtering.
The circuit generates the interlaced output fields by scaling
down the input frames with different offsets for odd and
even fields. Increasing the YSKIP setting reduces the
anti-flicker function. A YSKIP value of 4095 switches it off;
see Table 94.
The programming is similar to the horizontal scaler. For the
re-interlacing, the resolutions of the offset registers are not
sufficient, so the weighting factors for the first lines can
also be adjusted. YINC = 0 sets the scaling factor to 1;
YIWGTO and YIWGTE must not be 0.
Due to the re-interlacing, the circuit can perform upscaling.
The maximum factor depends on the setting of the
anti-flicker function and can be derived from the formulae
given in Section 7.17.
Horizontal scaler
Vertical scaler and anti-flicker filter
SAA7102; SAA7103
Product specification