SAA7124WP PHILIPS [NXP Semiconductors], SAA7124WP Datasheet - Page 14

• Manufacturer Part Number: SAA7124WP
• Description: Digital Video Encoder ECO-DENC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Chrominance is modified in gain (programmable
separately for U and V), standard dependent burst is
inserted, before baseband colour signals are interpolated
from 6.75 MHz data rate to 27 MHz data rate. One of the
interpolation stages can be bypassed, thus providing a
higher colour bandwidth, which can be made use of for
Y and C output. For transfer characteristics of the
chrominance interpolation filter see Figs 7 and 8.
The amplitude of inserted burst is programmable in a
certain range, suitable for standard signals and for special
effects. Behind the succeeding quadrature modulator,
colour in 10-bit resolution is provided on subcarrier.
The numeric ratio between Y and C outputs is in
accordance with set standards.
C
Using this circuit, data in accordance with the specification
of Closed Caption or Extended Data Service, delivered by
the control interface, can be encoded (Line 21).
Two dedicated pairs of bytes (two bytes per field), each
pair preceded by run-in clocks and framing code, are
possible.
The actual line number where data is to be encoded in, can
be modified in a certain range.
Data clock frequency is in accordance with definition for
NTSC-M standard 32 times horizontal line frequency.
Data LOW at the output of the DACs corresponds to 0 IRE,
data HIGH at the output of the DACs corresponds to
approximately 50 IRE.
It is also possible to encode Closed Caption Data for 50 Hz
field frequencies at 32 times horizontal line frequency.
A
For more information contact your nearest Philips
Semiconductors sales office.
RGB processor
This block contains a dematrix in order to produce RED,
GREEN and BLUE signals to be fed to a SCART plug.
Before Y, Cb and Cr signals are de-matrixed, 2 times
oversampling for luminance and 4 times oversampling for
colour difference signals is performed. For transfer curves
of luminance and colour difference components of RGB
see Figs 11 and 12.
1996 Nov 07
NTI
LOSED CAPTION ENCODER
Digital Video Encoder (ECO-DENC)
-
TAPING
(SAA7124
ONLY
)
14
Output interface/DACs
In the output interface encoded both Y and C signals are
converted from digital-to-analog in 10-bit resolution.
Y and C signals are also combined to a 10-bit CVBS
signal.
RED, GREEN and BLUE signals (optionally Cr, Y, Cb) are
also converted from digital-to-analog, each providing a
9-bit resolution.
All output occurs with the same processing delay.
Absolute amplitudes at the input of the DAC for CVBS is
reduced by
maximum use of conversion ranges.
Depending on control bits YC_EN and DEMOFF, different
signal combinations are available at DACs #1 to #4.
YC_EN = DEMOFF = LOW is the default configuration
after reset.
Table 1 Control of DAC signals
Outputs of the DACs can be set together in two groups
(#1 and #2 by DOWNB, #3 and #4 by DOWNA) via
software control to minimum output voltage for either
purpose.
Synchronization
Synchronization of the ECO-DENC is able to operate in
two modes; slave mode and master mode.
In the slave mode, the circuit accepts synchronization
pulses at the bidirectional RCV1 port (or equivalently as
frame synchronization from “CCIR 656” data stream).
The timing and trigger behaviour related to RCV1 can be
influenced by programming the polarity and on-chip delay
of RCV1. Active slope of RCV1 defines the vertical phase
and optionally the odd/even and colour frame phase to be
initialized, it can be also used to set the horizontal phase.
If the horizontal phase is not to be influenced by RCV1, a
horizontal pulse needs to be supplied at the RCV2 pin
(or a horizontal synchronization from “CCIR 656” data
stream). Timing and trigger behaviour can also be
influenced for RCV2.
YC_EN
0
0
1
1
15
DEMOFF
16
0
1
0
1
with respect to Y and C DACs to make
SAA7124; SAA7125
DAC1 DAC2 DAC3 DAC4
CVBS
CVBS
VBS
VBS
Preliminary specification
Cr
R
C
C
CVBS CVBS
CVBS CVBS
G
Y
Cb
B