SAA7806H NXP [NXP Semiconductors], SAA7806H Datasheet - Page 18

• Manufacturer Part Number: SAA7806H
• Description: One chip automotive CD audio device
• Manufacturer: NXP [NXP Semiconductors]

Philips Semiconductors
9397 750 13697
Objective data sheet
6.6.3.1 Signal xclk
6.6.3.2 Sysclock domain
6.6.3.3 Bitclock domain
6.6.3.4 Ebuclock domain
Most internal clocks are derived from xclk. This clock is the output of the clock multiplier in
the analog part and has a fixed frequency of 67.7376 MHz = 8.4672 (crystal oscillator) x 8.
If a 16 MHz crystal is used, the crystal clock is divided by 2 inside the analog block.
Crystal selection is done via AnaClockPLLControl(Sel16).
The main part of the internal channel decoder blocks run on the sysclk or derivatives.
Sysclk is derived from xclk divided by 2 (50 % duty cycle) and can be further divided down
via register SysclockConfig(SYSDIV). This register also provides the possibility to power
down the majority of the clocks (for sleep mode). The choice of the sysclk frequency in an
application is determined by the expected input bit rate on the RF stream. The relation
between this incoming bitstream frequency f
f
This brings the constraint to 0.25 < f
The I
interface. In audio slave mode this clock needs to be programmed exactly at
44100
DAC. In master mode with gated bclk, bclk must be programmed at a higher rate than the
required outgoing bit rate for that disc speed, to avoid FIFO overflow in the decoder. (For
instance at N = 1, the incoming RF bit rate is 4.3218 MHz, which corresponds to an output
bit rate of 1.4112 MHz. This means that bclk > 1.4112 MHz is high enough when
I
The bclk division is selected via register BitClockConfig. Also bclk gating can be enabled
via the same register.
The EBU back-end runs on this clock. The EBU (or SPDIF) interface is only enabled
during audio slave mode. The ebuclk needs to be exactly 44100
1
There are a few other clocks controlled by the clock control block:
bit
2
•
•
S-bus-16 is chosen, while I
•
•
•
•
/f
sysclk
operation. Ebuclk division is selected via register EBUClockConfig.
The HF-PLL operation range is between 0.25
The decoder and error corrector throughput rate is limited to 1.7
The hf_clk is fixed at 67.7376 MHz, and is used to clock in the samples from the ADC,
which is clocked by the xclk with the same clock frequency
The bclk_in is the incoming I
programmed to receive bclk rather than transmitting it (programmed via register
IISConfig)
The CL1 clock can be used to monitor the CFLG and MEAS debug lines; the
frequency can be programmed via register CLClockConfig
The CL16 clock can be used to clock an external audio DAC or audio filter IC; the
frequency can be programmed via register CLClockConfig.
2
S-bus back-end logic runs on this clock. Bclk is also output as part of the I
2
ratio. There are 2 limiting factors:
16/24/32 Hz (depending on I
Rev. 01 — 20 June 2005
2
S-bus-32 requires at least 2.8224 MHz bclk.
2
S-bus bit clock, which is used when I
bit
/f
sysclk
2
S-bus-mode), to get a 1
bit
< 1.7
and the system clock is expressed in a
One chip automotive CD audio device
f
bit
/f
sysclk
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
and 2
64 = 2.8224 MHz for
data rate to the audio
f
bit
SAA7806
f
2
bit
/f
S-bus is
sysclk
/f
sysclk
.
.
2
S-bus
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