SAA7806H NXP [NXP Semiconductors], SAA7806H Datasheet - Page 41

• Manufacturer Part Number: SAA7806H
• Description: One chip automotive CD audio device
• Manufacturer: NXP [NXP Semiconductors]

Philips Semiconductors
9397 750 13697
Objective data sheet
Fig 24. I
WCLK
SYNC
DATA
bclk
2
EF
S-bus format 1; 16 clocks per word
6.6.7.8 Data output interfaces
6.6.7.9 I
D0
Table 11:
When upsampling is enabled, the audio data output rate on the I
four times higher than without upsampling. Therefore the I
frequency has to be four times higher. This means that the I
needs to be programmed to be four times higher speed then normally required for that
bit-rate when upsampling would be disabled.
Another result of the upsampling is that every sample will have 18 bits precision instead of
16 after the upsample filter. To make use of this extra bit-precision, the user should select
24-bit or 32-bit I
be output.
There are 3 interfaces via which data can be output from the channel decoder block.
All interfaces can be used at the same time if needed, although there are a few restrictions
on the EBU, see
The I
and 32-bit I
format can be selected in register IISFormat.
Compliant with the I
are all clocked on the falling edge of the I
D15 D14 D13
Pass band
-
-
-
-
2
•
•
•
S-bus interface
Main data can be output via I
Subcode can be output via the subcode interface
Main data + subcode can be output via EBU/SPDIF.
2
S-bus is a 6 wire interface (four main and two subcode). It supports 16-bit, 24-bit
Upsample filter frequency response
flag - MSB (1 is unreliable)
2
S-bus and EIAJ (Sony) modes. Timing is shown in
D12 D11 D10
2
S-bus format. When using 16-bit I
Section 6.6.7.10 “EBU interface” on page
2
S-bus specification, the I
Rev. 01 — 20 June 2005
D9
Stop band
35 kHz to 64 kHz
64 kHz to 68 kHz
68 kHz
69 kHz to 88 kHz
left
D8
2
S-bus
D7
2
D6
S-bus bit clock signal bclk.
2
…continued
D5
S-bus signals WCLK, DATA, EF and SYNC
One chip automotive CD audio device
2
D4
S-bus format, the 2 lowest bits will not
flag - LSB
D3
2
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
S-bus word clock (pin WCLK)
42.
2
D2
Attenuation
S-bus bit clock (bclk) speed
50 dB
31 dB
35 dB
40 dB
Figure
D1
2
S-bus interface will be
D0
SAA7806
24. The required
flag - MSB
D15 D14
right
001aab768
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