CY8C20X37 CYPRESS [Cypress Semiconductor], CY8C20X37 Datasheet
CY8C20X37
Related parts for CY8C20X37
CY8C20X37 Summary of contents
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... Internal main oscillator (IMO): 6/12/24 MHz ❐ Note 1. Contact your nearest Cypress sales office for details. Cypress Semiconductor Corporation Document Number: 001-69257 Rev. *F CY8C20x37/37S/47/47S/67/67S 1.8 V CapSense SmartSense™ Auto-tuning – Internal low-speed oscillator (ILO kHz for watchdog ❐ and sleep timers RC crystal oscillator ❐ ...
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... Internal Low Speed Oscillator ( ILO) ( IMO) Multiple Clock Sources CapSense Module Internal POR SPI System Voltage and Master/ Resets References LVD Slave SYSTEM RESOURCES CY8C20x37/37S/47/47S/67/67S 1.8/2.5/3 V PWRSYS Port 0 [2] LDO (Regulator) Sleep and Watchdog Analog Reference Analog Mux Three 16- Bit Digital Programmable Clocks ...
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... ADC Electrical Specifications .................................... 18 DC POR and LVD Specifications .............................. 19 DC Programming Specifications ............................... 19 DC I2C Specifications ............................................... 20 Shield Driver DC Specifications ................................ 20 Document Number: 001-69257 Rev. *F CY8C20x37/37S/47/47S/67/67S DC IDAC Specifications ............................................ 20 AC Chip-Level Specifications .................................... 21 AC General Purpose I/O Specifications .................... 22 AC Comparator Specifications .................................. 22 AC External Clock Specifications .............................. 22 AC Programming Specifications ................................ 23 AC I2C Specifications ...
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... A common, versatile bus allows connection between I/O and the analog system. Each CY8C20x37/47/67/S PSoC device includes a dedicated CapSense block that provides sensing and scanning control circuitry for capacitive sensing applications. Depending on the PSoC package GPIOs are also included. The GPIOs provide access to the MCU and analog mux ...
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... Technical Support For assistance with technical issues, search KnowledgeBase articles and forums at www.cypress.com/support. If you cannot find an answer to your question, create a technical support case or call technical support at 1-800-541-4736. for the CY8C20x37/ Select Development available online at ...
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... Document Number: 001-69257 Rev. *F CY8C20x37/37S/47/47S/67/67S Organize and Connect You build signal chains at the chip level by interconnecting user modules to each other and the I/O pins. You perform the selection, configuration, and routing so that you have complete control over all on-chip resources ...
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... Pinouts The CY8C20x37/47/67/S PSoC device is available in a variety of packages, which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of digital I/O and connection to the common analog bus. However, V are not capable of digital I/O. 16-pin SOIC (12 Sensing Inputs) Table 1. Pin Definitions – ...
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... Alternate SPI clock. Document Number: 001-69257 Rev. *F [6] Description SDA, SPI MISO, P1[5] [ SCL, SPI [ SDA, SPI [8] CY8C20x37/37S/47/47S/67/67S Figure 3. CY8C20237, CY8C20247/S Device AI , XOut, P2[5] 1 P0[ XIn, P2[3] QFN XRES 11 (Top View SCL, SPI SS, P1[ ...
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... Figure 4. CY8C20337, CY8C20347/S Device Description AI, I2C SCL, SPI SS, P1[7] AI, I2C SDA, SPI MISO, P1[5] [10 SCL, SPI [10 SDA, SPI ) for best mechanical, thermal, and electrical performance. If not connected to ground, SS CY8C20x37/37S/47/47S/67/67S P0[2], AI AI, XOut, P2[ AI, XIn, P2[3] P0[0 QFN P2[4], AI AI, P2[ ...
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... Driven Shield Output (optional) [12] 2 P1[0] ISSP DATA , I C SDA, SPI [13] CLK V Supply ground SS [12] 2 P1[1] ISSP CLK , I C SCL, SPI MOSI P1[3] SPI CLK CY8C20x37/37S/47/47S/67/67S Figure 5. CY8C20767, CY8C20747 30-ball WLCSP Bottom View Top View Page ...
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... Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I alternate pins if you encounter issues. 16. Alternate SPI clock. Document Number: 001-69257 Rev. *F CY8C20x37/37S/47/47S/67/67S [14] Figure 6. CY8C20437, CY8C20447/S, CY8C20467/S Device Description ...
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... IOH I P0[ IOH I P0[3] 47 Power V 48 IOH I P0[1] CP Power V ) for best mechanical, thermal, and electrical performance. If not connected to ground, SS CY8C20x37/37S/47/47S/67/67S P2[ P2[1] 5 QFN P4[ P4[ (Top View P3[ P3[5] ...
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... Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C20x37/47/67/S PSoC devices. For the latest electrical specifications, confirm that you have the most recent datasheet by visiting the web at 5.5 V 1.71 V Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. ...
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... DD is captured. The rate is configured through the PSSDC bits in the SLP_CFG register. For the referenced DD goes lower than 1 edge rates slower than 1 V/ms. DD exceeds 5% of the base V , the rate at which CY8C20x37/37S/47/47S/67/67S Min Typ Max 1.71 – 5. °C, – ...
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... ILLVT5.5 set, Enable for Port1 V Input High Voltage with low threshold enable IHLVT5.5 set, Enable for Port1 Document Number: 001-69257 Rev. *F CY8C20x37/37S/47/47S/67/67S 85 ° 2.4 V and –40 °C Conditions – < 10 A, maximum source I OH ...
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... Port pins with LDO regulator Disabled for Port 1 V High output voltage OH4 Port Pins with LDO Regulator Disabled for Port 1 Document Number: 001-69257 Rev. *F CY8C20x37/37S/47/47S/67/67S Conditions – < 10 A, maximum source I OH current in all I/ 0.2 mA, maximum ...
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... P0[3] and P1[5]) – – – – Package and pin dependent temp = 25 C Conditions – – is 1.8 V GND Conditions Maximum voltage limited to V – – CY8C20x37/37S/47/47S/67/67S Min Typ Max – – 0.40 – – 0.30 × V 0.65 × V – – DD – 80 – ...
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... Offset error OFFSET E Gain error GAIN Power I Operating current ADC PSRR Power supply rejection ratio Document Number: 001-69257 Rev. *F CY8C20x37/37S/47/47S/67/67S DD Conditions Min 50 mV overdrive – Valid from 0 1.5 V – Average DC current – overdrive Power supply rejection ratio – ...
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... ILP Driving internal pull-down resistor IHP See appropriate DC GPIO Specifications on page 15. For V > 3V use V DD OH4 Table 10 on page 15. Erase/write cycles per block Following maximum Flash write cycles; ambient temperature of 55 °C CY8C20x37/37S/47/47S/67/67S Min Typ Max 1.61 1.66 1.71 – 2.36 2.41 – 2.60 2.66 – 2.82 2 ...
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... Pull-up resistors on I2C interface cannot be connected to a supply voltage that is more than 0.7 V higher than the CY8C20xx7/S/H/L power supply. See the CY8C20xx7 Silicon Errata document for more details. Document Number: 001-69257 Rev. *F CY8C20x37/37S/47/47S/67/67S 85 ° 2.4 V and –40 °C Conditions 3.1 V ≤ ...
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... MHz IMO long term N cycle-to-cycle jitter (RMS MHz IMO period jitter (RMS) Note 28. The minimum required XRES pulse length is longer when programming the device (see 29. See the Cypress Jitter Specifications application note, Document Number: 001-69257 Rev. *F CY8C20x37/37S/47/47S/67/67S Conditions – – – – – ...
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... Table 26. AC External Clock Specifications Symbol Description F Frequency (external oscillator OSCEXT frequency) High period Low period Power-up IMO to switch Document Number: 001-69257 Rev. *F CY8C20x37/37S/47/47S/67/67S Conditions Normal strong mode Port 3.0 to 3.6 V, 10 1.71 to 3.0 V, 10 3.0 to 3.6 V, 10% to 90% ...
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... XRES event, XRESINI based on 8 ILO clocks Note 30. Valid from °C. See the spec, CY8C20X66, CY8C20X46, CY8C20X36, CY7C643XX, CY7C604XX, CY8CTST2XX, CY8CTMG2XX, CY8C20X67, CY8C20X47, CY8C20X37, Programming Spec Document Number: 001-69257 Rev. *F Figure 10. AC Waveform T FSCLK T T SSCLK ...
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... Standard-Mode I rmax SU;DAT Document Number: 001-69257 Rev SDA and SCL Pins Description 2 C-bus system, but the requirement t 2 C-bus specification) before the SCL line is released. CY8C20x37/37S/47/47S/67/67S Standard Fast Mode Mode Min Max Min 0 100 0 4.0 – ...
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... Figure 12. SPI Master Mode 0 and SETUP HOLD MSB T T OUT_SU OUT_H Figure 13. SPI Master Mode 1 and SETUP HOLD MSB T T OUT_SU OUT_H MSB CY8C20x37/37S/47/47S/67/67S Min Typ Max – – 6 – – 3 – 50 – 60 – – 100 – – 40 – ...
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... OUT_H SS_MISO T T SETUP HOLD MSB Figure 15. SPI Slave Mode 1 and 3 T SS_CLK T OUT_H T SCLK_MISO SS_MISO MSB T T SETUP HOLD MSB CY8C20x37/37S/47/47S/67/67S Min Typ Max – – – – 42 – – 30 – – 50 – – – – 153 – ...
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... Packaging Information This section illustrates the packaging specifications for the CY8C20x37/47/67 PSoC device, along with the thermal impedances for each package. Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www ...
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... Document Number: 001-69257 Rev. *F CY8C20x37/37S/47/47S/67/67S Figure 18. 24-Pin (4 × 4 × 0.6 mm) QFN Figure 19. 32-Pin (5 × 5 × 0.6 mm) QFN 001-13937 *D 001-42168 *D Page ...
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... For information on the preferred dimensions for mounting QFN packages, see the following Application Note at ■ http://www.amkor.com/products/notes_papers/MLFAppNote.pdf. Pinned vias for thermal conduction are not required for the low power PSoC device. ■ Document Number: 001-69257 Rev. *F CY8C20x37/37S/47/47S/67/67S Figure 20. 48-Pin (6 × 6 × 0.6 mm) QFN 001-57280 *C Page ...
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... Typical C/W 33 C/W 21 C/W 20 C/W 18 C/W 54 C/W Package Capacitance 3.2 pF 3.3 pF Maximum Time above 260 C 260 C 260 C 260 C 260 C 260 C CY8C20x37/37S/47/47S/67/67S – 5 seconds 30 seconds 30 seconds 30 seconds 30 seconds 30 seconds Page ...
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... Three programming module cards ■ MiniProg programming unit ■ PSoC Designer software CD ■ Getting Started guide ■ USB 2.0 cable ■ CY8C20x37/37S/47/47S/67/67S Cypress Online Cypress Online allows you to program PSoC devices features an evaluation board and Cypress Online features a modular Page Store. Store. ...
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... Foot kit includes surface mount feet that can be soldered to the target PCB. 37. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at http://www.emulation.com. Document Number: 001-69257 Rev. *F CY8C20x37/37S/47/47S/67/67S CY3207 programmer unit ■ PSoC ISSP software CD ■ ...
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... Ordering Information The following table lists the CY8C20x37/47/67/S PSoC devices' key package features and ordering codes. Table 35. PSoC Device Key Features and Ordering Information Ordering Code CY8C20237-24SXI 16-pin SOIC CY8C20247-24SXI 16-pin SOIC CY8C20247S-24SXI 16-pin SOIC CY8C20237-24LKXI 16-pin QFN CY8C20237-24LKXIT 16-pin QFN (Tape and Reel) ...
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... LK = 16-pin QFN (no center pad 24-pin QFN, 32-pin QFN, 48-pin QFN FD = 30-ball WLCSP Speed grade = 24 MHz S = SmartSense™ Auto-tuning Enabled Part Number Family Code Technology Code CMOS Marketing Code PSoC Company ID Cypress CY8C20x37/37S/47/47S/67/67S CapSense Digital I/O XRES Analog [38] Sensors Pins Inputs 31 ...
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... SS slave select USB universal serial bus WLCSP wafer level chip scale package Document Number: 001-69257 Rev. *F CY8C20x37/37S/47/47S/67/67S Reference Documents ■ Technical reference manual for CY20xx7 devices ■ In-system Serial Programming (ISSP) protocol for 20xx7 ■ Host Sourced Serial Programming for 20xx7 devices ...
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... The conversion of all sensor capacitances to digital values. Period required to prepare a device, machine, process, or system for ready to function. The ratio between a capacitive finger signal and system noise. Serial peripheral interface is a synchronous serial data link standard. CY8C20x37/37S/47/47S/67/67S Page ...
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... Updated AC Chip-Level Specifications and its details). Updated Ordering Information 02/16/2012 Added CY8C20x37/37S/47/47S/67/67S part numbers and changed title to “1.8 V CapSense® Controller with SmartSense™ Auto-tuning 31 Buttons, 6 Sliders” Updated Features. Modified comparator blocks in Replaced SmartSense with SmartSense auto-tuning. Added CY8C20xx7S part numbers in Pin Definitions. ...
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... Document History Page Document Title: CY8C20x37/37S/47/47S/67/67S, 1.8 V CapSense 31 Buttons, 6 Sliders Document Number: 001-69257 *F 3645807 DST/BVI Document Number: 001-69257 Rev. *F ® Controller with SmartSense™ Auto-tuning 07/03/2012 Updated F parameter in the SCLK page 26 Changed OUT_HIGH OUT_H page 25 Updated Features section, “Programmable pin configurations” bullet: Included the following sub-bullet point - ■ ...
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... Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-69257 Rev. *F All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB Revised July 3, 2012 CY8C20x37/37S/47/47S/67/67S PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 ...