CY8C20X37 CYPRESS [Cypress Semiconductor], CY8C20X37 Datasheet - Page 11

• Manufacturer Part Number: CY8C20X37
• Manufacturer: CYPRESS [Cypress Semiconductor]

32-pin QFN (26 Sensing Inputs)
Table 5. Pin Definitions – CY8C20437, CY8C20447/S, CY8C20467/S
Document Number: 001-69257 Rev. *F
Notes
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CP
Pin
No.
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
14. The center pad (CP) on the QFN package must be connected to ground (V
15. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
16. Alternate SPI clock.
it must be electrically floated and not connected to any other signal.
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I
alternate pins if you encounter issues.
Digital
IOHR
IOHR
IOHR
IOHR
IOHR
IOHR
IOHR
IOHR
IOH
IOH
IOH
IOH
IOH
IOH
IOH
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Power
Power
Power
Power
Type
Input
Analog
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
P0[1]
P2[5]
P2[3]
P2[1]
P4[3]
P3[3]
P3[1]
P1[7]
P1[5]
P1[3]
P1[1]
V
P1[0]
P1[2]
P1[4]
P1[6]
XRES Active high external reset with
P3[0]
P3[2]
P4[0]
P4[2]
P2[0]
P2[2]
P2[4]
P0[0]
P0[2]
P0[4]
P0[6]
V
P0[7]
P0[3]
V
V
Name
SS
DD
SS
SS
Integrating input
Crystal output (XOut)
Crystal input (XIn)
I
I
SPI CLK.
ISSP CLK
MOSI.
Ground connection
ISSP DATA
SPI CLK
Driven Shield Output (optional)
Optional external clock input
(EXTCLK)
internal pull-down
Driven Shield Output (optional)
Driven Shield Output (optional)
Driven Shield Output (optional)
Driven Shield Output (optional)
Integrating input
Ground connection
Center pad must be connected to
ground
2
2
C SCL, SPI SS
C SDA, SPI MISO
[16]
Description
[15]
[15]
, I
, I
2
C SCL, SPI
2
C SDA,
SS
) for best mechanical, thermal, and electrical performance. If not connected to ground,
Figure 6.
AI , I2 C SCL, SPI SS, P1[7]
[14]
CY8C20x37/37S/47/47S/67/67S
CY8C20437, CY8C20447/S, CY8C20467/S Device
AI , XOut
AI , XIn
AI
AI
AI , P4[3]
AI , P3[3]
AI , P3[1]
, P0[1]
, P2[5]
, P2[3]
, P2[1]
1
2
3
4
5
6
7
8
(Top View)
QFN
24
23
22
21
20
19
18
17
Page 11 of 39
2
P2[4] , AI
P2[2] , AI
P2[0] , AI
P4[2] , AI
P4[0] , AI
P3[2] , AI
P3[0] , AI
C bus. Use
XRES