CY8C20X37 CYPRESS [Cypress Semiconductor], CY8C20X37 Datasheet - Page 14

• Manufacturer Part Number: CY8C20X37
• Manufacturer: CYPRESS [Cypress Semiconductor]

DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 9. DC Chip-Level Specifications
Document Number: 001-69257 Rev. *F
V
I
I
I
I
I
I
Notes
DD24
DD12
DD6
SB0
SB1
SBI2C
20. When V
21. If powering down in standby sleep mode, to properly detect and recover from a V
22. For proper CapSense block functionality, if the drop in V
DD
slower than 1 V/500 µs to avoid triggering POR. The only other restriction on slew rates for any other voltage range or transition is the SR
a. Bring the device out of sleep before powering down.
b. Assure that V
c. Set the No Buzz bit in the OSC_CR0 register to keep the voltage monitoring circuit powered during sleep.
d. Increase the buzz rate to assure that the falling edge of V
registers, refer to the
conditions to be detected and resets the device when V
be between 1.8 V and 5.5 V.
Symbol
[20, 21, 22]
DD
remains in the range from 1.71 V to 1.9 V for more than 50 µs, the slew rate when moving from the 1.71 V to 1.9 V range to greater than 2 V must be
DD
Supply voltage
Supply current, IMO = 24 MHz Conditions are V
Supply current, IMO = 12 MHz Conditions are V
Supply current, IMO = 6 MHz
Deep sleep current
Standby current with POR, LVD
and sleep timer
Standby current with I
enabled
falls below 100 mV before powering back up.
Technical Reference
Description
Manual. In deep sleep/standby sleep mode, additional low power voltage monitoring circuitry allows V
2
C
DD
DD
DD
goes lower than 1.1 V at edge rates slower than 1 V/ms.
exceeds 5% of the base V
See table
page 19
CPU = 24 MHz. CapSense running at 12 MHz,
no I/O sourcing current
CPU = 12 MHz. CapSense running at
12 MHz, no I/O sourcing current
Conditions are V
CPU = 6 MHz. CapSense running at 6 MHz,
no I/O sourcing current
V
V
Conditions are V
CPU = 24 MHz
is captured. The rate is configured through the PSSDC bits in the SLP_CFG register. For the referenced
DD
DD
 3.0 V, T
 3.0 V, T
DC POR and LVD Specifications on
A
A
= 25 °C, I/O regulator turned off
= 25 °C, I/O regulator turned off
Conditions
DD
DD
DD
DD
DD
brown out condition any of the following actions must be taken:
 3.0 V, T
 3.0 V, T
 3.0 V, T
= 3.3 V, T
DD
, the rate at which V
A
A
A
A
CY8C20x37/37S/47/47S/67/67S
= 25 °C,
= 25 °C,
= 25 °C,
= 25 °C and
DD
drops should not exceed 200 mV/s. Base V
1.71
Min
–
–
–
–
–
–
2.88
1.71
1.16
0.10
1.07
1.64
Typ
–
POWER_UP
DD
Max
5.50
4.00
2.60
1.80
1.50
Page 14 of 39
1.1
brown out
–
parameter.
DD
Units
mA
mA
mA
A
A
A
can
V