CY8C20X37 CYPRESS [Cypress Semiconductor], CY8C20X37 Datasheet - Page 24

• Manufacturer Part Number: CY8C20X37
• Manufacturer: CYPRESS [Cypress Semiconductor]

AC I
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 28. AC Characteristics of the I
Document Number: 001-69257 Rev. *F
f
t
t
t
t
t
t
t
t
t
Notes
SCL
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
SU;STO
BUF
SP
31. To wake up from sleep using I2C hardware address match event, I2C interface needs 20 ns hold time on SDA line with respect to falling edge of SCL. See the
32. A Fast-Mode I
Symbol
CY8C20xx7 Silicon Errata document for more details.
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line t
2
C Specifications
[31]
SCL clock frequency
Hold time (repeated) START condition. After this period, the first clock pulse is
generated
LOW period of the SCL clock
HIGH Period of the SCL clock
Setup time for a repeated START condition
Data hold time
Data setup time
Setup time for STOP condition
Bus free time between a STOP and START condition
Pulse width of spikes are suppressed by the input filter
2
C-bus device can be used in a standard mode I
rmax
+ t
SU;DAT
Figure 11. Definition for Timing for Fast/Standard Mode on the I
= 1000 + 250 = 1250 ns (according to the Standard-Mode I
2
C SDA and SCL Pins
Description
2
C-bus system, but the requirement t
2
C-bus specification) before the SCL line is released.
CY8C20x37/37S/47/47S/67/67S
SU;DAT
 250 ns must then be met. This automatically be the
Min
250
4.0
4.7
4.0
4.7
4.0
4.7
20
0
–
Standard
2
C Bus
Mode
Max
3.45
100
–
–
–
–
–
–
–
–
100
Fast Mode
Min
0.6
1.3
0.6
0.6
0.6
1.3
20
0
0
[32]
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Max
0.90
400
50
–
–
–
–
–
–
–
Units
kHz
µs
µs
µs
µs
µs
ns
µs
µs
ns