MPC106ARX66CE MOTOROLA [Motorola, Inc], MPC106ARX66CE Datasheet - Page 27

• Manufacturer Part Number: MPC106ARX66CE
• Description: PCI Bridge/Memory Controller
• Manufacturer: MOTOROLA [Motorola, Inc]

1.9 Document Revision History
Table 15 lists significant changes between revisions of this document.
Document
Revision
Rev 0
Rev 1
Rev 2
Rev 3
Rev 4
Rev 5
Initial release
Changed VCO maximum frequency in Table 6 to 200 MHz
Changed input and Hi-Z leakage current in Table 4. from 10µA to 15µA
Changed I
the sign and reduce the current to worst case value for the lowest strength default driver
Changed footnote 4 to Table 6 to be consistent with SYSCLK jitter spec of 200ps
Modified Table 7, Figure 3, Table 8, and Figure 5 to clarify reference clock (60x Bus Clock or
SYSCLK) for input and output specifications
Changed Group I and Group II signals input setup requirement for 83 MHz in Table 7 from 3.0 ns
to 3.5 ns min.
Changed Group I-IV (non-PCI signals) input hold requirement (Spec 11a) in Table 7 from 1.0 ns
to 0 ns
Changed Group V and VI (PCI signals) input hold requirement (Spec 11b) in Table 7 from 1.0ns
to -0.5ns
Changed output valid times for all non-PCI signals (Specs 13a, 13b and 14a) from 8 ns to 7 ns at
66 Mhz and from 7 ns to 6 ns at 83 MHz
Corrected Figure 10 to reflect TOE signal is shared with DBG1 on pin U5
Changed input and Hi-Z leakage current, V
Changed the power consumption data in Table 5
Changed note 7 of Table 8 to show the minimum timing specification assumes CL=0 pF
Deleted PLL[0-3] = 0010 from Table 11 to remove 1:1 mode operation between 16MHz and
25MHz
Added note 10 to Table 8 regarding PCI hold time
Lowered PCI 3.3V signalling output high voltage from 3.0 V to 2.7V and added current conditions
for PCI 3.3V VOH and VOL in Table 4 to reflect current production test
Included note 12 in Specification 10c of Table 4; Clarified note 9 in Table 8 and included in
Specification 12 and 18; Added a similar “guaranteed by design and not tested” note to Table 9
and included in Specifications 3, 7, and 11. All to reflect current production test.
Corrected Figure 12 dimensions from TBD to actual die size
Table 1 and Table 2 include notes on extended temperature parts.
Table 8, Note 8 changed to include: “These values are guaranteed by design and are not tested.”
Added PNS references below Table 1 and Table 6. Changed footnote ordering in Table 8,
Table 9, and Table 10. Added new footnote 2 to Table 6. Changed part number key.
MPC106 PCI Bridge/Memory Controller Hardware Specifications
OH
and I
Table 15. Document Revision History
OL
in Table 4 from 18mA and 14mA respectively to -7mA and 7mA to correct
Substantive Change(s)
in
in Table 4 from 5.5V to 3.3V
Document Revision History
27