PIC18F23K20 MICROCHIP [Microchip Technology], PIC18F23K20 Datasheet - Page 213

• Manufacturer Part Number: PIC18F23K20
• Description: 28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

17.4.3.4
An SSP Mask (SSPMSK) register is available in I
Slave mode as a mask for the value held in the
SSPSR register during an address comparison
operation. A zero (‘0’) bit in the SSPMSK register has
the effect of making the corresponding bit in the
SSPSR register a “don’t care”.
This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
SSP operation until written with a mask value.
REGISTER 17-7:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-1
bit 0
Note 1: The MSK0 bit is used only in 10-bit slave mode. In all other modes, this bit has no effect.
R/W-1
MSK7
SSP Mask Register
MSK<7:1>: Mask bits
1 = The received address bit n is compared to SSPADD<n> to detect I
0 = The received address bit n is not used to detect I
MSK<0>: Mask bit for I
I
1 = The received address bit 0 is compared to SSPADD<0> to detect I
0 = The received address bit 0 is not used to detect I
2
C Slave mode, 10-bit Address (SSPM<3:0> = 0111):
R/W-1
MSK6
SSPMSK: SSP MASK REGISTER
W = Writable bit
‘1’ = Bit is set
R/W-1
MSK5
2
C Slave mode, 10-bit Address
R/W-1
MSK4
2
C
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-1
MSK3
This register must be initiated prior to setting
SSPM<3:0> bits to select the I
10-bit address).
The SSP Mask register is active during:
• 7-bit Address mode: address compare of A<7:1>.
• 10-bit Address mode: address compare of A<7:0>
PIC18F2XK20/4XK20
only. The SSP mask has no effect during the
reception of the first (high) byte of the address.
2
2
C address match
(1)
C address match
R/W-1
MSK2
2
2
C address match
C address match
x = Bit is unknown
R/W-1
MSK1
2
C Slave mode (7-bit or
DS41303G-page 213
MSK0
R/W-1
(1)
bit 0