PIC18F23K20 MICROCHIP [Microchip Technology], PIC18F23K20 Datasheet - Page 244

• Manufacturer Part Number: PIC18F23K20
• Description: 28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2XK20/4XK20
18.1.2.9
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Get the received 8 Least Significant data bits
11. If an overrun occurred, clear the OERR flag by
DS41303G-page 244
Initialize the SPBRGH:SPBRG register pair and
the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 18.3 “EUSART
Baud Rate Generator (BRG)”).
Set the RX/DT and TX/CK TRIS controls to ‘1’.
Enable the serial port by setting the SPEN bit
and the RX/DT pin TRIS bit. The SYNC bit must
be clear for asynchronous operation.
If interrupts are desired, set the RCIE interrupt
enable bit and set the GIE and PEIE bits of the
INTCON register.
If 9-bit reception is desired, set the RX9 bit.
Set the DTRXP if inverted receive polarity is
desired.
Enable reception by setting the CREN bit.
The RCIF interrupt flag bit will be set when a
character is transferred from the RSR to the
receive buffer. An interrupt will be generated if
the RCIE interrupt enable bit was also set.
Read the RCSTA register to get the error flags
and, if 9-bit data reception is enabled, the ninth
data bit.
from the receive buffer by reading the RCREG
register.
clearing the CREN receiver enable bit.
Asynchronous Reception Set-up:
18.1.2.10
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Read the RCSTA register to get the error flags.
11. Get the received 8 Least Significant data bits
12. If an overrun occurred, clear the OERR flag by
13. If the device has been addressed, clear the
Initialize the SPBRGH, SPBRG register pair and
the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 18.3 “EUSART
Baud Rate Generator (BRG)”).
Set the RX/DT and TX/CK TRIS controls to ‘1’.
Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
If interrupts are desired, set the RCIE interrupt
enable bit and set the GIE and PEIE bits of the
INTCON register.
Enable 9-bit reception by setting the RX9 bit.
Enable address detection by setting the ADDEN
bit.
Set the DTRXP if inverted receive polarity is
desired.
Enable reception by setting the CREN bit.
The RCIF interrupt flag bit will be set when a
character with the ninth bit set is transferred
from the RSR to the receive buffer. An interrupt
will be generated if the RCIE interrupt enable bit
was also set.
The ninth data bit will always be set.
from the receive buffer by reading the RCREG
register. Software determines if this is the
device’s address.
clearing the CREN receiver enable bit.
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
9-bit Address Detection Mode Set-up
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