PIC18F23K20 MICROCHIP [Microchip Technology], PIC18F23K20 Datasheet - Page 349
PIC18F23K20
Manufacturer Part Number
PIC18F23K20
Description
28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F23K20.pdf
(456 pages)
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Part Number:
PIC18F23K20T-I/SO
Manufacturer:
Microchip Technology
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RRNCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example 1:
Example 2:
2010 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
REG
REG
W
REG
W
REG
Q1
=
=
=
=
=
=
register ‘f’
Rotate Right f (No Carry)
RRNCF
0 f 255
d [0,1]
a [0,1]
(f<n>) dest<n – 1>,
(f<0>) dest<7>
N, Z
The contents of register ‘f’ are rotated
one bit to the right. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank will be
selected (default), overriding the BSR
value. If ‘a’ is ‘1’, then the bank will be
selected as per the BSR value.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
RRNCF
RRNCF
Read
0100
Q2
1101 0111
1110 1011
?
1101 0111
1110 1011
1101 0111
f {,d {,a}}
REG, 1, 0
REG, 0, 0
00da
Process
Data
Q3
register f
ffff
destination
Write to
Q4
ffff
SETF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
PIC18F2XK20/4XK20
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
REG
Q1
register ‘f’
Set f
SETF
0 f 255
a [0,1]
FFh f
None
The contents of the specified register
are set to FFh.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
SETF
Read
0110
Q2
=
=
f {,a}
5Ah
FFh
100a
Process
REG, 1
Data
Q3
DS41303G-page 349
ffff
register ‘f’
Write
Q4
ffff
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