MC68HC705C4ACB MOTOROLA [Motorola, Inc], MC68HC705C4ACB Datasheet - Page 144

• Manufacturer Part Number: MC68HC705C4ACB
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Serial Peripheral Interface (SPI)
Technical Data
144
SPI — SPI Enable Bit
MSTR — Master Bit
CPOL — Clock Polarity Bit
CPHA — Clock Phase Bit
SPR1 and SPR0 — SPI Clock Rate Bits
This read/write bit enables the SPI. Reset clears the SPE bit.
This read/write bit selects master mode operation or slave mode
operation. Reset clears the MSTR bit.
This read/write bit determines the logic state of the PD4/SCK pin
between transmissions. To transmit data between SPIs, the SPIs
must have identical CPOL bits. Reset has no effect on the CPOL bit.
This read/write bit controls the timing relationship between the serial
clock and SPI data. To transmit data between SPIs, the SPIs must
have identical CPHA bits. When CPHA = 0, the PD5/SS pin of the
slave SPI must be set to logic 1 between bytes. Reset has no effect
on the CPHA bit.
These read/write bits select the master mode serial clock rate, as
shown in
no effect on the serial clock. Reset has no effect on SPR1 and SPR0.
1 = SPI enabled
0 = SPI disabled
1 = Master mode
0 = Slave mode
1 = PD4/SCK pin at logic 1 between transmissions
0 = PD4/SCK pin at logic 0 between transmissions
1 = Edge following first active edge on PD4/SCK latches data
0 = First active edge on PD4/SCK latches data
Serial Peripheral Interface (SPI)
Table
SPR[1:0]
Table 11-1. SPI Clock Rate Selection
00
01
10
11
11-1. The SPR1 and SPR0 bits of a slave SPI have
MC68HC705C4A • MC68HSC705C4A — Rev. 3.0
Internal Clock
Internal Clock
Internal Clock
Internal Clock
SPI Clock Rate
16
32
2
4
MOTOROLA