ISP1563BM PHILIPS [NXP Semiconductors], ISP1563BM Datasheet - Page 32

• Manufacturer Part Number: ISP1563BM
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
9397 750 14224
Product data sheet
8.2.3.6 Data register
Table 38:
Address: Value read from address 34h + 6h
Table 39:
[1]
The Data register is an optional, 1 B register that provides a mechanism for the function to
report state dependent operating data, such as power consumed or heat dissipated.
Table 40
Table 40:
Address: Value read from address 34h + 7h
Legend: * reset value
Bit
7
6
5 to 0
Originating device’s
bridge PM state
D0
D1
D2
D3
D3
Bit
7 to 0 DATA[7:0] R
hot
cold
PM: Power Management.
Symbol
shows the bit description of the register.
PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions register bit
description
PCI bus power and clock control
Data register bit description
Symbol
BPCC_EN
B2_B3#
reserved
[1]
Access
Secondary bus
PM state
B0
B1
B2
B2, B3
B3
Rev. 01 — 14 July 2005
Value
00h*
Description
Bus Power/Clock Control Enable:
1 — Indicates that the bus power or clock control mechanism as
defined in
0 — Indicates that the bus or power control policies as defined in
Table 39
When the Bus Power or Clock Control mechanism is disabled, the
bridge’s PMCSR Power State (PS) field cannot be used by the
system software to control the power or clock of the bridge’s
secondary bus.
B2/B3 support for D3
action that is to occur as a direct result of programming the
function to D3
1 — Indicates that when the bridge function is programmed to
D3
0 — Indicates that when the bridge function is programmed to
D3
This bit is only meaningful if bit 7 (BPCC_EN) is logic 1.
-
[1]
hot
hot
, its secondary bus’s PCI clock will be stopped (B2).
, its secondary bus will have its power removed (B3).
Description
DATA: This register is used to report the state dependent
data requested by the D_S field of the PMCSR register.
The value of this register is scaled by the value reported
by the DS field of the PMCSR register.
are disabled.
Resultant actions by bridge (either direct or indirect)
none
none
clock stopped on secondary bus
clock stopped and PCI V
bus (B3 only); for definition of B2_B3#, see
none
Table 39
hot
.
is enabled.
hot
: The state of this bit determines the
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
HS USB PCI Host Controller
CC
removed from secondary
ISP1563
Table
32 of 107
38.