ISP1563BM PHILIPS [NXP Semiconductors], ISP1563BM Datasheet - Page 73

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ISP1563BM

Manufacturer Part Number
ISP1563BM
Description
Hi-Speed Universal Serial Bus PCI Host Controller
Manufacturer
PHILIPS [NXP Semiconductors]
Datasheet

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Philips Semiconductors
Table 100: HCCPARAMS - Host Controller Capability Parameters register bit allocation
Address: Value read from func2 of address 10h + 08h
9397 750 14224
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
11.3.3 HCCPARAMS register
31
23
15
R
R
R
R
0
0
0
7
0
The Host Controller Capability Parameters (HCCPARAMS) register is a 4 B register, and
the bit allocation is given in
Table 101: HCCPARAMS - Host Controller Capability Parameters register bit description
Address: Value read from func2 of address 10h + 08h
Bit
31 to 8
7 to 4
30
22
14
R
R
R
R
0
0
0
6
0
IST[3:0]
Symbol
reserved
IST[3:0]
29
21
13
R
R
R
R
0
0
0
5
0
Rev. 01 — 14 July 2005
Table
Description
-
Isochronous Scheduling Threshold: Default = implementation
dependent. This field indicates, relative to the current position of the
executing Host Controller, where software can reliably update the
isochronous schedule. When IST[3] is logic 0, the value of the least
significant three bits indicates the number of micro frames a Host
Controller can hold a set of isochronous data structures, one or
more, before flushing the state. When IST[3] is logic 1, the host
software assumes the Host Controller may cache an isochronous
data structure for an entire frame.
28
20
12
R
R
R
R
0
0
0
4
1
100.
reserved
reserved
reserved
27
19
11
R
R
R
R
0
0
0
3
0
reserved
26
18
10
R
R
R
R
0
0
0
2
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
HS USB PCI Host Controller
PFLF
25
17
R
R
R
R
0
0
9
0
1
1
ISP1563
64AC
73 of 107
24
16
R
R
R
R
0
0
8
0
0
0

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