LAN83C185_03 SMSC [SMSC Corporation], LAN83C185_03 Datasheet - Page 53

• Manufacturer Part Number: LAN83C185_03
• Description: High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver
• Manufacturer: SMSC [SMSC Corporation]

High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
SMSC LAN83C185
5.6
5.6.1
5.6.2
General Description
The “DSP Block” includes the following modules:
DSP Core (Equalizer, Timing and BLW correction), Testability / Configuration module (Testability /
Configuration control), Testability / Configuration Registers (not including any SMI registers) and the
Multiplexers (for the testability / configuration signals).
The details of the DSP core are described in the DSP architecture specification. The Testability /
Configuration features give access to the status and control of most of the internal registers in the DSP.
The status and control mechanisms are described in the architecture specification.
ADC Gray code converting
The LAN83C185 ADC generates a 6 bit “modified” Gray code. Normal Gray code outputs number in
the range of 0 to 2
The MLT3 analog input has a voltage range of –1V to +1V. It is necessary to translate this to -32 to
+31 on the output of the ADC. Thus the Gray Code is modified by offsetting it by -32. This is translated
to 2’s complement before being presented to the DSP.
DSP Block
n
– 1. The 6-bit code generates numbers from 0 to 63 (decimal).
DATASHEET
45
Rev. 0.6 (12-12-03)