LAN9118_05 SMSC [SMSC Corporation], LAN9118_05 Datasheet - Page 74
LAN9118_05
Manufacturer Part Number
LAN9118_05
Description
High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.LAN9118_05.pdf
(126 pages)
- Current page: 74 of 126
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Revision 1.1 (05-17-05)
5.3.8
31-16
14-13
BITS
BITS
13-3
12-8
7-0
15
14
15
[31]
0
0
1
1
DESCRIPTION
Reserved.
Force TX Status Discard (TXS_DUMP). This self-clearing bit clears the TX
status FIFO of all pending status DWORD’s. When a ‘1’ is written, the TX
status pointers are cleared to zero.
Force TX Data Discard (TXD_DUMP). This self-clearing bit clears the TX
data FIFO of all pending data. When a ‘1’ is written, the TX data pointers
are cleared to zero.
Reserved
Force RX Discard (RX_DUMP). This self-clearing bit clears the RX data
and status FIFOs of all pending data. When a ‘1’ is written, the RX data
and status pointers are cleared to zero.
Note:
Reserved
RX Data Offset (RXDOFF). This field controls the offset value, in bytes,
that is added to the beginning of an RX data packet. The start of the valid
data will be shifted by the number of bytes specified in this field. An offset
of 0-31 bytes is a valid number of offset bytes.
Note:
Reserved
TX_CFG—Transmit Configuration Register
This register controls the transmit functions on the LAN9118 Ethernet Controller.
Offset:
Please refer to section “Force Receiver Discard (Receiver
Dump)” on page 54 for a detailed description regarding the use
of RX_DUMP.
The two LSBs of this field (D[9:8]) must not be modified while
the RX is running. The receiver must be halted, and all data
purged before these two bits can be modified. The upper three
bits (DWORD offset) may be modified while the receiver is
running. Modifications to the upper bits will take affect on the
next DWORD read.
[30]
0
1
0
1
Table 5.2 RX Alignment Bit Definitions
DESCRIPTION
70h
DATASHEET
74
High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Size:
16-byte alignment
32-byte alignment
4-byte alignment
End Alignment
Reserved
32 bits
TYPE
TYPE
R/W
SC
RO
RO
RO
SC
SC
RO
SMSC LAN9118
DEFAULT
DEFAULT
00000
Datasheet
0
0
0
-
-
-
-
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