FDC37B72X_07 SMSC [SMSC Corporation], FDC37B72X_07 Datasheet - Page 133

• Manufacturer Part Number: FDC37B72X_07
• Description: 128 Pin Enhanced Super I/O Controller with ACPI Support
• Manufacturer: SMSC [SMSC Corporation]

Bit 0 of Port 92, which generates the nALT_RST
signal, is used to reset the CPU under program
control. This signal is AND’ed together externally
with the reset signal (nKBDRST) from the
keyboard controller to provide a software means
of resetting the CPU.
means of reset than is provided by the keyboard
controller. Writing a 1 to bit 0 in the Port 92
Register causes this signal to pulse low for a
minimum of 6µs, after a delay of a minimum of
14µs. Before another nALT_RST pulse can be
generated, bit 0 must be set to 0 either by a
Bit
7:6
5
4
3
2
1
0
Function
Reserved. Returns 00 when read
Reserved. Returns a 1 when read
Reserved. Returns a 0 when read
Reserved. Returns a 0 when read
Reserved. Returns a 1 when read
ALT_A20 Signal control. Writing a 0 to this bit causes the ALT_A20 signal to be
driven low. Writing a 1 to this bit causes the ALT_A20 signal to be driven high.
Alternate System Reset. This read/write bit provides an alternate system reset
function. This function provides an alternate means to reset the system CPU to
effect a mode switch from Protected Virtual Address Mode to the Real Address
Mode. This provides a faster means of reset than is provided by the Keyboard
controller. This bit is set to a 0 by a system reset. Writing a 1 to this bit will cause
the nALT_RST signal to pulse active (low) for a minimum of 1 µs after a delay of
500 ns. Before another nALT_RST pulse can be generated, this bit must be written
back to a 0.
This provides a faster
8042
P21
0
0
1
1
Port 92 Register
nGATEA20
ALT_A20
133
0
1
0
1
system reset of a write to Port 92. Upon reset,
this signal is driven inactive high (bit 0 in the Port
92 Register is set to 0).
If Port 92 is enabled, i.e., bit 2 of KRST_GA20 is
set to 1, then a pulse is generated by writing a 1
to bit 0 of the Port 92 Register and this pulse is
AND’ed with the pulse generated from the 8042.
This pulse is output on pin KRESET and its
polarity is controlled by the GPI/O polarity
configuration.
System
nA20M
0
1
1
1