FDC37B72X_07 SMSC [SMSC Corporation], FDC37B72X_07 Datasheet - Page 69
FDC37B72X_07
Manufacturer Part Number
FDC37B72X_07
Description
128 Pin Enhanced Super I/O Controller with ACPI Support
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.FDC37B72X_07.pdf
(238 pages)
- Current page: 69 of 238
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The chip incorporates two full function UARTs.
They are compatible with the NS16450, the 16450
ACE registers and the NS16C550A. The UARTS
perform serial-to-parallel conversion on received
characters and parallel-to-serial conversion on
transmit
independently programmable from 460.8K baud
down to 50 baud.
programmable for 1 start; 1, 1.5 or 2 stop bits;
even, odd, sticky or no parity; and prioritized
interrupts.
programmable baud rate generator that is capable
of dividing the input clock or crystal by a number
from 1 to 65535. The UARTs are also capable of
supporting the MIDI data rate. Refer to the
Configuration
disabling, power down and changing the base
address of the UARTs.
UART is enabled by programming OUT2 of that
UART
The following section describes the operation of the registers.
characters.
The
*Note: DLAB is Bit 7 of the Line Control Register
DLAB*
Registers
to
X
X
X
X
X
X
X
0
0
0
1
1
UARTs
The character options are
The
A2
0
0
0
0
0
0
1
1
1
1
0
0
The interrupt from a
for
TABLE 32 - ADDRESSING THE SERIAL PORT
each
a
data
information
A1
0
0
0
1
1
1
0
0
1
1
0
0
contain
SERIAL PORT (UART)
rates
A0
logic
0
0
1
0
0
1
0
1
0
1
0
1
are
on
a
69
Receive Buffer (read)
Transmit Buffer (write)
Interrupt Enable (read/write)
Interrupt Identification (read)
FIFO Control (write)
Line Control (read/write)
Modem Control (read/write)
Line Status (read/write)
Modem Status (read/write)
Scratchpad (read/write)
Divisor LSB (read/write)
Divisor MSB (read/write
"1". OUT2 being a logic "0" disables that UART's
interrupt. The second UART also supports IrDA
1.0, HP-SIR and ASK-IR infrared modes of
operation.
Note: The UARTs may be configured to share an
interrupt. Refer to the Configuration section for
more information.
REGISTER DESCRIPTION
Addressing of the accessible registers of the Serial
Port is shown below. The configuration registers
(see Configuration section) define the base
addresses of the serial ports.
registers are located at sequentially increasing
addresses above these base addresses. The chip
contains two serial ports, each of which contain a
register set as described below.
REGISTER NAME
The Serial Port
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